ADC08351 Datasheet, PDF (6/25 Pages) National Semiconductor (TI) – 8-Bit, 42 MSPS, 40 mW A/D Converter

ADC08351
SNAS026E – JUNE 2000 – REVISED MARCH 2013
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Converter Electrical Characteristics (continued)
The following specifications apply for V_A = V_D = +3.0 V_DC, V_REF = 2.4V, V_IN = 1.63 V_P-P, OE = 0V, C_L = 20 pF, f_CLK = 42 MHz,
50% duty cycle, unless otherwise specified.
Boldface limits apply for T_A = T_MIN to T_MAX: all other limits T_A = 25°C⁽¹⁾⁽²⁾
Symbol
Parameter
Conditions
Typical⁽³⁾ Limits⁽³⁾
Units
(Limits)
CLK, OE Digital Input Characteristics
V_IH
Logical High Input Voltage
V_IL
Logical Low Input Voltage
I_IH
Logical High Input Current
I_IL
Logic Low Input Current
C_IN
Logic Input Capacitance
Digital Output Characteristics
V_D = V_A = 3V
V_D = V_A = 3V
V_IH = V_D = V_A = 3.3V
V_IL = 0V, V_D = V_A = 3.3V
2.0
V (min)
1.0
V (max)
10
µA
−10
µA
10
pF
I_OH
High Level Output Current
I_OL
Low Level Output Current
V_OH
High Level Output Voltage
V_OL
Low Level Output Voltage
I_OZH,
I_OZL
TRI-STATE Output Current
AC Electrical Characteristics
V_D = 2.7V, V_OH = V_D −0.5V
V_D = 2.7V, OE = DGND, V_OL = 0.4V
V_D = 2.7V, I_OH = −360 µA
V_D = 2.7V, I_OL = 1.6 mA
OE = V_D = 3.3V, V_OH = 3.3V or V_OL = 0V
−1.1
mA (min)
1.8
mA (min)
2.65
V
0.2
V
±10
µA
f_C1
Maximum Conversion Rate
f_C2
Minimum Conversion Rate
t_OD
Output Delay
Pipline Delay (Latency)
CLK High to Data Valid
42
MHz (min)
2
MHz
14
19
ns (max)
2.5
Clock Cycles
t_DS
t_OH
t_EN
t_DIS
ENOB
Sampling (Aperture) Delay
Output Hold Time
OE Low to Data Valid
OE High to High Z State
Effective Number of Bits
SINAD Signal-to-Noise & Distortion
SNR
Signal-to-Noise Ratio
THD
Total Harmonic Distortion
SFDR
Spurious Free Dynamic Range
CLK Low to Acquisition of Data
CLK High to Data Invalid
Loaded as in Figure 20
Loaded as in Figure 20
f_CLK = 30 MHz, f_IN = 1 MHz
f_CLK = 42 MHz, f_IN = 4.4 MHz
f_CLK = 42 MHz, f_IN = 21 MHz
f_CLK = 30 MHz, f_IN = 1 MHz
f_CLK = 42 MHz, f_IN = 4.4 MHz
f_CLK = 42 MHz, f_IN = 21 MHz
f_CLK = 30 MHz, f_IN = 1 MHz
f_CLK = 42 MHz, f_IN = 4.4 MHz
f_CLK = 42 MHz, f_IN = 21 MHz
f_CLK = 30 MHz, f_IN = 1 MHz
f_CLK = 42 MHz, f_IN = 4.4 MHz
f_CLK = 42 MHz, f_IN = 21 MHz
f_CLK = 30 MHz, f_IN = 1 MHz
f_CLK = 42 MHz, f_IN = 4.4 MHz
f_CLK = 42 MHz, f_IN = 21 MHz
2
ns
9
ns
14
ns
10
ns
7.2
Bits
7.2
Bits
6.8
6.1
Bits (min)
45
dB
45
dB
43
38.5
dB (min)
44
dB
45
dB
44
41
dB (min)
−57
dB
−51
dB
−46
−41
dB (min)
57
dB
54
dB
49
41
dB (min)
6
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