74AC11646_09 Datasheet, PDF (6/9 Pages) Texas Instruments – OCTAL BUS TRANSCEIVER AND REGISTER WITH 3-STATE OUTPUTS

74AC11646
OCTAL BUS TRANSCEIVER AND REGISTER
WITH 3ĆSTATE OUTPUTS
SCAS079A − JULY 1987 − REVISED APRIL 1993
timing requirements over recommended operating free-air temperature range, V_CC = 3.3 V ± 0.3 V
(unless otherwise noted) (see Figure 2)
fclock
tw
tsu
th
Clock frequency
Pulse duration, CLK high or low
Setup time, A or B before CLKAB↑ or CLKBA↑
Hold time, A or B after CLKAB↑ or CLKBA↑
TA = 25°C
MIN MAX
0
65
7.7
6.5
1
MIN MAX UNIT
0
65 MHz
7.7
ns
6.5
ns
1
ns
timing requirements over recommended operating free-air temperature range, V_CC = 5 V ± 0.5 V
(unless otherwise noted) (see Figure 2)
fclock
tw
tsu
th
Clock frequency
Pulse duration, CLK high or low
Setup time, A or B before CLKAB↑ or CLKBA↑
Hold time, A or B after CLKAB↑ or CLKBA↑
TA = 25°C
MIN MAX
0 100
5
4.5
1
MIN MAX UNIT
0 100 MHz
5
ns
4.5
ns
1
ns
switching characteristics over recommended operating free-air temperature range,
V_CC = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 2)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
TA = 25°C
MIN
MIN TYP MAX
fmax
65
65
tPLH
tPHL
A or B
B or A
1.5 9.1 12.1 1.5
1.5 10.7 13.4 1.5
tPZH
OE
tPZL
A or B
1.5
13 16.4 1.5
1.5 16.1 20.4 1.5
tPHZ
OE
tPLZ
A or B
1.5 7.9 9.6 1.5
1.5 7.2 8.9 1.5
tPLH
tPHL
CLKBA or CLKAB
A or B
1.5 11.8
15 1.5
1.5 13.7 16.8 1.5
tPLH
tPHL
SBA or SAB†
(A or B high)
A or B
1.5 9.8 12.9 1.5
1.5
12 14.5 1.5
tPLH
tPHL
SBA or SAB†
(A or B low)
A or B
1.5 10.7 13.8 1.5
1.5 12.4
15 1.5
tPZH
DIR
tPZL
A or B
1.5 13.7 17.1 1.5
1.5 16.8
21 1.5
tPHZ
DIR
tPLZ
A or B
1.5 7.9 9.7 1.5
1.5 7.3 9.1 1.5
† _{These parameters are measured with the internal output state of the storage register opposite to that of the bus input.}
MAX
13.8
14.5
18.7
21.8
10.3
9.6
17
18.3
14.4
15.8
15.4
16.4
19.4
23.6
10.5
9.9
UNIT
MHz
ns
ns
ns
ns
ns
ns
ns
ns
2−6
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