TRF7964A Datasheet, PDF (59/76 Pages) Texas Instruments – MULTI-PROTOCOL FULLY INTEGRATED 13.56-MHz RFID READER/WRITER IC

TRF7964A
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SLOS787A – MAY 2012 – REVISED JUNE 2012
6.3.2.9 RX Special Setting Register (Address 0x0A)
Table 6-13. RX Special Setting Register (Address 0x0A)
Function: Sets the gains and filters directly
Default: 0x40 at POR = H or EN = L, and at each write to the ISO Control register 0x01. When bits B7, B6, B5 and B4 are all zero, the
filters are set for ISO14443B (240 kHz to 1.4 MHz).
Bit
Name
Function
Description
B7
C212
Bandpass 110 kHz to 570 kHz Appropriate for 212-kHz subcarrier system (FeliCa)
B6
C424
Bandpass 200 kHz to 900 kHz Appropriate for 424-kHz subcarrier used in ISO15693
B5
M848
Bandpass 450 kHz to 1.5 MHz
Appropriate for Manchester-coded 848-kHz subcarrier used in ISO14443A
and B
B4
hbt
Bandpass 100 kHz to 1.5 MHz
Gain reduced for 18 dB
Appropriate for highest bit rate (848 kbps) used in high-bit-rate ISO14443
B3
gd1
00 = Gain reduction 0 dB
B2
gd2
01 = Gain reduction for 5 dB
10 = Gain reduction for 10 dB
Sets the RX gain reduction, and reduces sensitivity
11 = Gain reduction for 15 dB
AGC activation level changed from five times the digitizing level to three
B1
agcr
AGC activation level change
times the digitizing level.
1 = 3x
0 = 5x
AGC action can be done any time during receive process. It is not limited
B0
no-lim
AGC action is not limited in time
to the start of receive ("max hold").
1 = continuously – no time limit
0 = 8 subcarrier pulses
The first four steps of the AGC control are comparator adjustment. The second three steps are real gain
reduction done automatically by AGC control. The AGC is turned on after TX.
The first gain and filtering stage following the RF envelope detector has a nominal gain of 15 and the 3-dB
band-pass frequencies are adjustable in the range from 100 kHz to 400 kHz for high pass and 600 kHz to
1.5 MHz for low pass. The next gain and filtering stage has a nominal gain of 8 and the frequency
characteristic identical to first stage. The filter setting is done automatically with internal preset for each
new selection of communication standard in ISO Control register (0x01). Additional corrections can be
done by directly writing into the RX Special Setting register 0x0A.
The second receiver gain stage and digitizer stage are included in the AGC loop. The AGC loop can be
activated by setting the bit B2 = 1 (agc-on) in Chip Status Control register 0x00. If activated the AGC
monitors the signal level at the input of digitizing stage. If the signal level is significantly higher than the
digitizing threshold level, the gain reduction is activated. The signal level, at which the action is started, is
by default five times the digitizing threshold level. It can be reduced to three times the digitizing level by
setting bit B1 = 1 (agcr) in RX Special Setting register (0x0A).
The AGC action is fast and it typically finishes after four subcarrier pulses. By default the AGC action is
blocked after first few pulses of subcarrier signal so AGC cannot interfere with signal reception during rest
of data packet. In certain cases, this is not optimal, so this blocking can be removed by setting B0 = 1
(no_lim) in RX Special Setting register (0x0A).
NOTE
The setting of bits B4, B5, B6 and B7 to zero selects bandpass characteristic of 240 kHz to
1.4 MHz. This is appropriate for ISO14443B, FeliCa protocol, and ISO14443A higher bit
rates 212 kbps and 424 kbps.
Copyright © 2012, Texas Instruments Incorporated
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