TPS65983B Datasheet, PDF (59/112 Pages) Texas Instruments – USB Type-C and USB PD Controller, Power Switch, and High Speed Multiplexer

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TPS65983B
SLVSDM6A – OCTOBER 2016 – REVISED OCTOBER 2016
9.3.8 System Glue Logic
The system glue logic module performs various system interface functions such as control of the system
interface for RESETZ, MRESET, and VOUT_3V3. This module supports various hardware timers for digital
control of analog circuits.
9.3.9 Power Reset Congrol Module (PRCM)
The PRCM implements all clock management, reset control, and sleep mode control.
9.3.10 Interrupt Monitor
The Interrupt Control module handles all interrupt from the external GPIO as well as interrupts from internal
analog circuits.
9.3.11 ADC Sense
The ADC Sense module is a digital interface to the SAR ADC. The ADC converts various voltages and currents
from the analog circuits. The ADC converts up to 11 channels from analog levels to digital signals. The ADC can
be programmed to convert a single sampled value.
9.3.12 UART
Two digital UARTS are provided for serial communication. The inputs to the UART are selectable by a
programmable digital crossbar multiplexer. The UART may act as pass-through between the system and the
Type-C port or may filter through the digital core. The UART_RX/TX pins are typically used to daisy chain
multiple TPS65983Bs in series to share application code at startup.
9.3.13 I²C Slave
Two I²C interfaces provide interface to the digital core from the system. These interfaces are master/slave
configurable and support low-speed and full-speed signaling. See the I²C Slave Interface section for more
information.
9.3.14 SPI Master
The SPI master provides a serial interface to an external flash memory. The recommended memory is the
W25Q80DV 8 Mbit Serial Flash Memory. A memory of at least 2 Mbit is required when the TPS65983B is using
the memory in an unshared manner. A memory of at least 8 Mbit is required when the TPS65983B is using the
memory in an shared manner. See theSPI Master Interface section for more information.
9.3.15 Single-Wire Debugger Interface
The SWD interface provides a mechanism to directly master the digital core.
9.3.16 DisplayPort HPD Timers
To enable DisplayPort HPD signaling through PD messaging, two GPIO pins (GPIO4, GPIO5) are used as the
HPD input and output. When events occur on this pins during a DisplayPort connection through the Type-C
connector (configured in firmware), hardware timers trigger and interrupt the digital core to indicated needed PD
messaging. Table 5 shows each I/O function when GPIO4/5 are configured in HPD mode. When HPD is not
enabled via firmware, both GPIO4 and GPIO5 remain generic GPIO and may be programmed for other functions.
Figure 52 and Figure 53.
Table 5. HPD GPIO Configuration
HPD (Binary) Configuration
00
01
10
11
GPIO4
HPD TX
HPD RX
HPD TX
HPD TX/RX (bidirectional)
GPIO5
Generic GPIO
Generic GPIO
HPD RX
Generic GPIO
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