TAS5760M Datasheet, PDF (59/84 Pages) Texas Instruments – Check for Samples: TAS5760M

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TAS5760M
SLOS772D – JULY 2013 – REVISED JULY 2015
10.2.6 Stereo BTL Using Hardware Control, 32-Pin DAP Package Option
System Processor
&
Associated Passive
Components
1.0 UF
HIGH Æ fSPK_AMP = 8 * fS
LOW Æ fSPK_AMP = 16 * fS
RCLIP2
VDD
10 l3
VDD
1.0 UF
1
1.0 UF
2
1.0 UF ³
4
5
6
7
8
9
10
11
Gain Set by Pin Decode
12
13
14
15
16
RCLIP1
AVDD
GVDD_REG 48
SFT_CLIP
GGND
47
ANA_REG
BSTRPA+ 46
VCOM
SPK_OUTA+ 31
ANA_REF
PVDD
30
SPK_FAULT
PGND
29
SPK_SD
SPK_OUTA- 28
FREQ/SDA
BSTRPA- 27
PBTL/SCL
BSTRPB- 26
DVDD
SPK_OUTB- 25
SPK_GAIN0
PGND
24
SPK_GAIN1
PVDD
23
SPK_SLEEP/ADR SPK_OUTB+ 22
MCLK
BSTRPB+ 21
SCLK
DGND
20
SDIN
LRCK
19
1.0 UF
0.22UF
0.22UF
0.22UF
0.22UF
PVDD
0.1 UF
470 UF
0.1 UF
LFILT
CFILT
CFILT
LFILT
LFILT
CFILT
CFILT
LFILT
Figure 56. Stereo BTL using Hardware Control, 32-Pin DAP Package Option
10.2.6.1 Design Requirements
For this design example, use the parameters listed in Table 19 as the input parameters.
PARAMETER
Low Power Supply
High Power Supply
Host Processor
Output Filters
Speakers
Table 19. Design Parameters
EXAMPLE
3.3 V
5 V to 24 V
I2S Compliant Master
GPIO Control
Inductor-Capacitor Low Pass Filter
4 Ω to 8 Ω
10.2.6.2 Detailed Design Procedure
10.2.6.2.1 Startup Procedures- Hardware Control Mode
1. Configure all hardware pins as required by the application using PCB connections (that is PBTL, FREQ,
GAIN, etc.)
2. Start with SPK_SD pin pulled LOW and SPK_SLEEP/ADR pin pulled HIGH
3. Bring up power supplies (it does not matter if PVDD/AVDD or DVDD comes up first, provided the device is
held in shutdown.)
4. Once power supplies are stable, start MCLK, SCLK, LRCK
5. Once power supplies and clocks are stable and all hardware control pins have been configured, bring
SPK_SD HIGH
6. Once the device is out of shutdown mode, bring SPK_SLEEP/ADR LOW
7. The device is now in normal operation
10.2.6.2.2 Shutdown Procedures- Hardware Control Mode
1. The device is in normal operation
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