DLPA3005 Datasheet, PDF (59/75 Pages) Texas Instruments – PMIC and High-Current LED Driver IC

www.ti.com
DLPA3005
DLPS071 – OCTOBER 2015
9.1 Power-Up and Power-Down Timing
The power-up and power-down sequence is important to ensure a correct operation of the DLPA3005 and to
prevent damage to the DMD. The DLPA3005 controls the correct sequencing of the DMD_VRESET,
DMD_VBIAS, and DMD_VOFFSET to ensure a reliable operation of the DMD.
The general startup sequence of the supplies is described earlier in Supply and Monitoring. The power-up
sequence of the high voltage DMD lines is especially important in order not to damage the DMD. A too large
delta voltage between DMD_VBIAS and DMD_VOFFSET could cause the damage and should therefore be
prevented.
After PROJ_ON is pulled high, the DMD buck converters and LDOs are powered (PWR1-4) the DMD high
voltage lines (HV) are sequentially enabled. First DMD_VOFFSET is enabled. After a delay
VOFS_STATE_DURATION (register 0x10) DMD_VBIAS is enabled. Finally, again after a delay
VBIAS_STATE_DURATION (register 0x11) DMD_VRESET is enabled. Now the DLPA3005 is fully powered and
ready for starting projection.
For power down there are two sequences, normal power down (Figure 27) and a fault fast power down used in
case a fault occurs (Figure 28).
In normal power down mode, the power down is initiated after pulling PROJ_ON pin low. 25 ms after PROJ_ON
is pulled low, first DMD_VBIAS and DMD_VRESET stop regulating, 10 ms later followed by DMD_OFFSET.
When DMD_OFFSET stopped regulating, RESET_Z is pulled low. 1 ms after the DMD_OFFSET stopped
regulating, all three voltages are discharged. Finally, all other supplies are turned off. INT_Z remains high during
the power down sequence since no fault occurred. During power down it is ensured that the HV levels do not
violate the DMD specifications on these three lines. For this it is important to select the capacitors such that
C_VOFFSET is equal to C_VRESET and C_VBIAS is ≤ C_VOFFSET, C_VBIAS.
The fast power down mode (Figure 28) is started in case a fault occurs (INT_Z will be pulled low), for instance
due to overheating. The fast power down mode can be enabled/ disabled via register 0x01,
FAST_SHUTDOWN_EN. By default the mode is enabled. After the fault occurs, regulation of DMD_VBIAS and
DMD_VRESET is stopped. The time (delay) between fault and stop of regulation can be controlled via register
0x0F (VBIAS/VRST_DELAY). The delay can be selected between 4 µs and ~1.1 ms, where the default is ~540
µs. A defined delay-time after the regulation stopped, all three high voltages lines are discharged and RESET_Z
is pulled low. The delay can be controlled via register 0x0F (VOFS/VRESETZ_DELAY). Delay can be selected
between 4 µs and ~1.1ms. The default is ~4 µs. Finally the internal DMD_EN signal is pulled low.
Copyright © 2015, Texas Instruments Incorporated
Submit Documentation Feedback
59