TLV320AIC3104-Q1 Datasheet, PDF (58/91 Pages) Texas Instruments – LOW-POWER STEREO AUDIO CODEC

TLV320AIC3104-Q1
SLAS715 – JUNE 2010
Table 8. Page 0/Register 36: ADC Flag Register
BIT READ/ RESET
WRITE VALUE
DESCRIPTION
D7
R
0
Left-ADC PGA Status
0: Applied gain and programmed gain are not the same.
1: Applied gain = programmed gain
D6
R
0
Left-ADC Power Status
0: Left ADC is in a power-down state.
1: Left ADC is in a power-up state.
D5
R
0
Left-AGC Signal Detection Status
0: Signal power is greater than or equal to noise threshold.
1: Signal power is less than noise threshold.
D4
R
0
Left-AGC Saturation Flag
0: Left AGC is not saturated.
1: Left-AGC gain applied = maximum allowed gain for left AGC
D3
R
0
Right-ADC PGA Status
0: Applied gain and programmed gain are not the same.
1: Applied gain = programmed gain
D2
R
0
Right-ADC Power Status
0: Right ADC is in a power-down state.
1: Right ADC is in a power-up state.
D1
R
0
Right-AGC Signal Detection Status
0: Signal power is greater than or equal to noise threshold.
1: Signal power is less than noise threshold.
D0
R
0
Right-AGC Saturation Flag
0: Right AGC is not saturated.
1: Right-AGC gain applied = maximum allowed gain for right AGC
BIT
D7
D6
D5–D4
D3–D0
Table 9. Page 0/Register 37: DAC Power and Output Driver Control Register
READ/
WRITE
R/W
R/W
R/W
R
RESET
VALUE
0
0
00
000
DESCRIPTION
Left-DAC Power Control
0: Left DAC is not powered up.
1: Left DAC is powered up.
Right-DAC Power Control
0: Right DAC is not powered up.
1: Right DAC is powered up.
HPLCOM Output Driver Configuration Control
00: HPLCOM configured as differential of HPLOUT
01: HPLCOM configured as constant VCM output
10: HPLCOM configured as independent single-ended output
11: Reserved. Do not write this sequence to these register bits.
Reserved. Write only zeros to these bits.
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