English
Language : 

AMC7812B Datasheet, PDF (58/92 Pages) TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS – 12-Bit Analog Monitoring and Control Solution with Multichannel ADC, DACs, and Temperature Sensors
AMC7812B
SBAS625A – SEPTEMBER 2013 – REVISED SEPTEMBER 2013
www.ti.com
Daisy-Chain Operation
For systems that contain several AMC7812Bs, the SDO pin can be used to daisy-chain multiple devices
together. This daisy-chain feature is useful in reducing the number of serial interface lines. The first CS falling
edge starts the operation cycle. SCLK is continuously applied to the input shift register when CS is low.
If more than 24 clock pulses are applied, data ripple out of the shift register and appear on the SDO line. These
data are clocked out on the SCLK rising edge and are valid on the falling edge. By connecting the SDO output of
the first device to the SDI input of the next device in the chain, a multiple-device interface is constructed. Each
device in the system requires 24 clock pulses. Therefore, the total number of clock cycles must equal 24N,
where N is the total number of AMC7812Bs in the daisy chain. When the serial transfer to all devices is
complete, CS is taken high. This action transfers data from the SPI shifter registers to the internal register of
each AMC7812B in the daisy-chain and prevents any further data from being clocked in. The serial clock can be
continuous or gated. A continuous SCLK source can only be used if CS is held low for the correct number of
clock cycles. In gated clock mode, a burst clock containing the exact number of clock cycles must be used and
CS must be taken high after the final clock in order to latch the data. Figure 108 to Figure 111 illustrate the daisy-
chain operation.
C
B
A
SDI
SDI-C SDO-C
SDI-B
SDO-B
SDI-A
SDO-A
SDO
CS
SCLK
Figure 108. Three AMC7812Bs in a Daisy-Chain Configuration
CS
SDI-C
SDO-C
SDI-B
SDO-B
SDI-A
SDO-A
Cycle 0
RA0 RB0 RC0
XX RA0 RB0
XX RA0 RB0
XX
XX RA0
XX
XX RA0
XX
XX
XX
Cycle 1
RA1
CD0
CD0
BD0
BD0
AD0
RB1
RA1
RA1
CD0
CD0
BD0
RC1
RB1
RB1
RA1
RA1
CD0
Cycle 2
RA2
CD1
CD1
BD1
BD1
AD1
RB2
RA2
RA2
CD1
CD1
BD1
RC2
RB2
RB2
RA2
RA2
CD1
RAn (RBn, RCn) = Read Command for Register N of device A (B,C)
ADn (BDn, CDn) = Data from Register N of device A (B, C)
XX = Don’t care, undefined
Figure 109. Reading Multiple Registers
Cycle 3
RA3
CD2
CD2
BD2
BD2
AD2
RB3
RA3
RA3
CD2
CD2
BD2
RC3
RB3
RB3
RA3
RA3
CD2
58
Submit Documentation Feedback
Product Folder Links: AMC7812B
Copyright © 2013, Texas Instruments Incorporated