ADS58J63 Datasheet, PDF (58/84 Pages) Texas Instruments – Quad-Channel, 14-Bit, 500-MSPS Telecom Receiver Device

ADS58J63
SBAS717A – JUNE 2015 – REVISED JUNE 2015
7.6.3.7 Interleaving Engine Page (6100h)
7.6.3.7.1 Register 18h (address = 18h) [reset = 0h], Interleaving Engine Page (6100h)
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Figure 113. Register 18h
A7-A0 in hex
D7
D6
D5
D4
D3
D2
INTERLEAVING ENGINE PAGE (6100h)
18
0
0
0
0
0
0
LEGEND: R/W = Read/Write; -n = value after reset
D1
D0
IL BYPASS
Bit Name
D1-D0 IL BYPASS
Table 38. Register 18h Field Descriptions
Type
R/W
Reset
00
Description
Allows bypassing of the interleaving correction. To be used when ADC
test patterns are enabled.
00 = interleaving correction enabled
11= interleaving correction bypassed
7.6.3.7.2 Register 68h (address = 68h) [reset = 0h], Interleaving Engine Page (6100h)
Figure 114. Register 68h
A7-A0 in hex
D7
D6
D5
D4
D3
D2
D1
D0
INTERLEAVING ENGINE PAGE (6100h)
68
0
0
0
0
0
DC CORR DIS
0
LEGEND: R/W = Read/Write; -n = value after reset
Bit Name
D2 DC CORR DIS
Table 39. Register 68h Field Descriptions
Type
R/W
Reset
0
Description
Enables DC offset correction loop.
00 = DC offset correction enabled
11 = DC offset correction disabled
Others = Do not use
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