TLV320AIC3262_15 Datasheet, PDF (57/84 Pages) Texas Instruments – TLV320AIC3262 Ultralow Power Stereo Audio Codec With miniDSP, DirectPath Headphone, and Stereo Class-D Speaker Amplifier

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TLV320AIC3262
SLAS679A – DECEMBER 2011 – REVISED SEPTEMBER 2015
TLV320AIC3262 is entirely controlled by registers. Reading and writing these registers is accomplished by an 8-
bit command sent to the MOSI pin of the part prior to the data for that register. The command is structured as
shown in Table 13. The first 7 bits specify the address of the register which is being written or read, from 0 to
127 (decimal). The command word ends with an R/W bit, which specifies the direction of data flow on the serial
bus. In the case of a register write, the R/W bit should be set to 0. A second byte of data is sent to the MOSI pin
and contains the data to be written to the register. Reading of registers is accomplished in a similar fashion. The
8-bit command word sends the 7-bit register address, followed by the R/W bit = 1 to signify a register read is
occurring. The 8- bit register data is then clocked out of the part on the MISO pin during the second 8 SCLK
clocks in the frame.
For more details see the TLV320AIC3262 Applications Reference Guide, SLAU309.
Figure 30. SPI Timing Diagram for Register Write
Figure 31. SPI Timing Diagram for Register Read
10.3.14.4 Digital Audio Interfaces
The TLV320AIC3262 features three digital audio data serial interfaces, or audio buses. Any of these digital audio
interfaces can be selected for playback and recording through the stereo DACs and stereo ADCs respectively.
This enables this audio codec to handle digital audio from different devices on a mobile platform. A common
example of this would be individual connections to an application processor, a communication baseband
processor, or a Bluetooth chipset. By utilizing the TLV320AIC3262 as the center of the audio processing in a
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