PCM5121_16 Datasheet, PDF (56/120 Pages) Texas Instruments – Audio Stereo DAC

PCM5121, PCM5122
SLAS763B – AUGUST 2012 – REVISED JANUARY 2016
Transmitter
Data Type
Table 40. Write Operation - Basic I²C Framework
M
M
M
S
M
S
M
S
St
slave address
R/
ACK DATA ACK DATA ACK
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S
M
ACK
Sp
Transmitter
Data Type
Table 41. Read Operation - Basic I²C Framework
M
M
M
S
S
M
S
M
St
slave address
R/
ACK DATA ACK DATA ACK
M = Master Device; S = Slave Device; St = Start Condition; Sp = Stop Condition
M
M
NACK Sp
8.4.1.1.2.4 Write Register
A master can write to any PCM512x registers using single or multiple accesses. The master sends a PCM512x
slave address with a write bit, a register address with auto-increment bit, and the data. If auto-increment is
enabled, the address is that of the starting register, followed by the data to be transferred. When the data is
received properly, the index register is incremented by 1 automatically. When the index register reaches 0x7F,
the next value is 0x0. Table 42 shows the write operation.
Transmitter
M
Data Type
St
M
slave addr
Table 42. Write Operation
M
S
M
S
M
S
M
S
W
ACK
inc
reg
addr
ACK
write
data 1
ACK
write
data 2
ACK
S
M
ACK Sp
M = Master Device; S = Slave Device; St = Start Condition; Sp = Stop Condition; W = Write; ACK =
Acknowledge
8.4.1.1.2.5 Read Register
A master can read the PCM512x register. The value of the register address is stored in an indirect index register
in advance. The master sends a PCM512x slave address with a read bit after storing the register address. Then
the PCM512x transfers the data which the index register points to. When auto-increment is enabled, the index
register is incremented by 1 automatically. When the index register reaches 0x7F, the next value is 0x0. Table 43
shows the read operation.
Table 43. Read Operation
Transmitter M
M
M
S
M
S
M
M
M
S
S
M
Data Type
St
slave
addr
W
ACK
inc
reg
addr
ACK
Sr
slave
addr
R
ACK data ACK
M
M
NACK Sp
M = Master Device; S = Slave Device; St = Start Condition; Sr = Repeated Start Condition; Sp = Stop Condition;
W = Write; R = Read; NACK = Not acknowledge
8.4.1.1.2.6 Timing Characteristics
SDA
START
t_BUF
t_D-SU
t_D-HD
Repeated
START
t_SDA-R
t_SDA-F
t_P-SU
STOP
t_LOW
t_SCL-R
t_{RS- HD}
t_SP
SCL
t_S-HD
t_SCL-F
t_HI
t_RS-SU
Figure 74. Register Access Timing
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