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MSP430F563X_11 Datasheet, PDF (56/106 Pages) Texas Instruments – MIXED SIGNAL MICROCONTROLLER
MSP430F563x
SLAS650B – JUNE 2010 – REVISED AUGUST 2011
www.ti.com
PMM, SVM Low Side
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN TYP
SVMLE = 0, PMMCOREV = 2
0
I(SVML)
SVML current consumption
SVMLE = 1, PMMCOREV = 2, SVMLFP = 0
200
SVMLE = 1, PMMCOREV = 2, SVMLFP = 1
2.0
SVMLE = 1, dVCORE/dt = 10 mV/µs,
SVMLFP = 1
2.5
tpd(SVML) SVML propagation delay
SVMLE = 1, dVCORE/dt = 1 mV/µs,
SVMLFP = 0
20
t(SVML)
SVML on/off delay time
SVMLE = 0→1,
SVMLFP = 1
SVMLE = 0→1,
SVMLFP = 0
12.5
100
MAX
UNIT
nA
nA
µA
µs
µs
Wake-Up From Low-Power Modes and Reset
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN TYP
Wake-up time from LPM2,
PMMCOREV = SVSMLRRL = n fMCLK ≥ 4 MHz
3
tWAKE-UP-FAST
LPM3, or LPM4 to active
mode (1)
(where n = 0, 1, 2, or 3),
SVSLFP = 1
1 MHz < fMCLK <
4 MHz
4
Wake-up time from LPM2,
PMMCOREV = SVSMLRRL = n
tWAKE-UP-SLOW LPM3 or LPM4 to active
(where n = 0, 1, 2, or 3),
150
mode (2)
SVSLFP = 0
tWAKE-UP-LPM5
Wake-up time from LPM3.5 or
LPM4.5 to active mode(3)
2
tWAKE-UP-RESET
Wake-up time from RST or
BOR event to active mode(3)
2
MAX
6.5
8.0
UNIT
µs
165 µs
3 ms
3 ms
(1) This value represents the time from the wakeup event to the first active edge of MCLK. The wakeup time depends on the performance
mode of the low side supervisor (SVSL) and low side monitor (SVML). Fastest wakeup times are possible with SVSLand SVML in full
performance mode or disabled when operating in AM, LPM0, and LPM1. Various options are available for SVSLand SVML while
operating in LPM2, LPM3, and LPM4. See the Power Management Module and Supply Voltage Supervisor chapter in the MSP430x5xx
Family User's Guide (SLAU208).
(2) This value represents the time from the wakeup event to the first active edge of MCLK. The wakeup time depends on the performance
mode of the low side supervisor (SVSL) and low side monitor (SVML). In this case, the SVSLand SVML are in normal mode (low current)
mode when operating in AM, LPM0, and LPM1. Various options are available for SVSLand SVML while operating in LPM2, LPM3, and
LPM4. See the Power Management Module and Supply Voltage Supervisor chapter in the MSP430x5xx Family User's Guide
(SLAU208).
(3) This value represents the time from the wakeup event to the reset vector execution.
Timer_A, Timers TA0, TA1, and TA2
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
Internal: SMCLK, ACLK
fTA
Timer_A input clock frequency
External: TACLK
Duty cycle = 50% ± 10%
VCC
1.8 V/ 3 V
MIN TYP
tTA,cap
Timer_A capture timing
All capture inputs.
Minimum pulse width required for
capture.
1.8 V/ 3 V
20
MAX UNIT
20 MHz
ns
Timer_B, Timer TB0
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
Internal: SMCLK, ACLK
fTB
Timer_B input clock frequency
External: TBCLK
Duty cycle = 50% ± 10%
VCC
1.8 V/ 3 V
MIN TYP
MAX UNIT
20 MHz
56
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