AWR1642 Datasheet, PDF (56/84 Pages) Texas Instruments – Single-Chip 77- and 79-GHz FMCW Radar Sensor

AWR1642
SWRS203 – MAY 2017
www.ti.com
6.3.1.1 Clock Subsystem
The AWR1642 clock subsystem generates 76 to 81 GHz from an input reference of 40-MHz crystal. It has
a built-in oscillator circuit followed by a clean-up PLL and a RF synthesizer circuit. The output of the RF
synthesizer is then processed by an X4 multiplier to create the required frequency in the 76- to 81-GHz
spectrum. The RF synthesizer output is modulated by the timing engine block to create the required
waveforms for effective sensor operation.
The clean-up PLL also provides a reference clock for the host processor after system wakeup.
The clock subsystem also has built-in mechanisms for detecting the presence of a crystal and monitoring
the quality of the generated clock.
Figure 6-1 describes the clock subsystem.
Self Test
RESYNTH
x4
MULT
Timing
Engine
Approx. 1 GHz
(fixed clock
domain)
Clean-
Up PLL
Lock Detect
SoC Clock
XO/
Slicer
CLK Detect
40 and 50 MHz
Figure 6-1. Clock Subsystem
56
Detailed Description
Submit Documentation Feedback
Product Folder Links: AWR1642
Copyright © 2017, Texas Instruments Incorporated