TUSB3410-Q1 Datasheet, PDF (55/94 Pages) Texas Instruments – USB To Serial Port Controller

UART
7.1.14 MASK: UART Interrupt-Mask Register (Addr:FFAB)
This register controls the UARTs interrupt sources.
7
6
5
4
3
2
1
0
RSV
RSV
RSV
RSV
RSV
RRIE
SIE
MIE
R/O
R/O
R/O
R/O
R/O
R/W
R/W
R/W
BIT
NAME RESET
FUNCTION
0 MIE
0 This bit controls the UART-modem interrupt.
MIE = 0 Modem interrupt is disabled
MIE = 1 Modem interrupt is enabled
1 SIE
0 This bit controls the UART-status interrupt.
SIE = 0 Status interrupt is disabled
MIE = 1 Status interrupt is enabled
2 TRI
0 This bit controls the UART-TxE/RxF interrupts.
TRIE = 0 TxE/RxF interrupts are disabled
TRIE = 1 TxE/RxF interrupts are enable
7−3 RSV
0 Reserved = 0
7.2 UART Data Transfer
Figure 7−2 illustrates the data transfer between the UART and the host using the DMA controller and the USB
buffer manager (UBM). A buffer of 512 bytes is reserved for buffering the UART channel (transmit and receive
buffers). The UART channel has 64 bytes of double-buffer space (X- and Y-buffer). When the DMA writes to
the X-buffer, the UBM reads from the Y-buffer. Similarly, when the DMA reads from the X-buffer, the UBM writes
to the Y-buffer. The DMA channel is configured to operate in the continuous mode (by setting DMACDR[CNT]
= 1). Once the MCU enables the DMA, data transfer toggles between the UMB and the DMA without MCU
intervention. See IN transaction (TUSB3410 to host) for DMA transfer-termination condition.
7.2.1 Receiver Data Flow
The UART receiver has a 32-byte FIFO. The receiver FIFO has two trigger levels. One is the high-level mark
(HALT), which is set to 12 bytes and the other is the low-level mark (RESUME), which is set to 4 bytes. When
the HALT mark is reached, either the RTS pin goes high or Xoff is transmitted (depending on the auto setting).
When the FIFO reaches the RESUME mark, then either the RTS pin goes low or Xon is transmitted.
46 TUSB3410-Q1
SGLS249A − August 2004 − Revised September 2008