LM3S1626 Datasheet, PDF (546/716 Pages) Texas Instruments – ARM and Thumb are registered trademarks and Cortex is a trademark

Inter-Integrated Circuit (I²C) Interface
14.1 Block Diagram
Figure 14-1. I²C Block Diagram
Interrupt
I²C Control
I2CMSA
I2CMCS
I2CMDR
I2CMTPR
I2CMIMR
I2CMRIS
I2CMMIS
I2CMICR
I2CMCR
I2CSOAR
I2CSCSR
I2CSDR
I2CSIM
I2CSRIS
I2CSMIS
I2CSICR
I²C Master Core
I2CSCL
I2CSDA
I²C Slave Core
I2CSCL
I2CSDA
I²C I/O Select
I2CSCL
I2CSDA
14.2
Signal Description
Table 14-1 on page 546 lists the external signals of the I²C interface and describes the function of
each. The I²C interface signals are alternate functions for some GPIO signals and default to be
GPIO signals at reset., with the exception of the I2C0SCL and I2CSDA pins which default to the
I²C function. The column in the table below titled "Pin Assignment" lists the possible GPIO pin
placements for the I²C signals. The AFSEL bit in the GPIO Alternate Function Select (GPIOAFSEL)
register (page 341) should be set to choose the I²C function. Note that the I²C pins should be set to
open drain using the GPIO Open Drain Select (GPIOODR) register. For more information on
configuring GPIOs, see “General-Purpose Input/Outputs (GPIOs)” on page 321.
Table 14-1. I2C Signals (64LQFP)
Pin Name
I2C0SCL
I2C0SDA
Pin Number
47
27
Pin Type
I/O
I/O
Buffer Type^a Description
OD
I²C module 0 clock.
OD
I²C module 0 data.
a. The TTL designation indicates the pin has TTL-compatible voltage levels.
14.3
Functional Description
The I²C module is comprised of both master and slave functions which are implemented as separate
peripherals. For proper operation, the SDA and SCL pins must be connected to bi-directional
open-drain pads. A typical I²C bus configuration is shown in Figure 14-2 on page 547.
See “Inter-Integrated Circuit (I²C) Interface” on page 666 for I²C timing diagrams.
546
November 17, 2011
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