LM3S1Z16 Datasheet, PDF (542/794 Pages) Texas Instruments – Stellaris® LM3S1Z16 Microcontroller

Analog-to-Digital Converter (ADC)
Register 9: ADC Sample Phase Control (ADCSPC), offset 0x024
This register allows the ADC module to sample at one of 16 different discrete phases from 0.0°
through 337.5°.
Note:
Care should be taken when the PHASE field is non-zero, as the resulting delay in sampling
the AINx input may result in undesirable system consequences. The time from ADC trigger
to sample is increased and could make the response time longer than anticipated. The
added latency could have ramifications in the system design. Designers should carefully
consider the impact of this delay.
ADC Sample Phase Control (ADCSPC)
ADC0 base: 0x4003.8000
Offset 0x024
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
PHASE
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit/Field
31:4
3:0
Name
reserved
PHASE
Type
Reset Description
RO 0x0000.000 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
R/W
0x0
Phase Difference
This field selects the sample phase difference from the standard sample
time.
Value Description
0x0 ADC sample lags by 0.0°
0x1 ADC sample lags by 22.5°
0x2 ADC sample lags by 45.0°
0x3 ADC sample lags by 67.5°
0x4 ADC sample lags by 90.0°
0x5 ADC sample lags by 112.5°
0x6 ADC sample lags by 135.0°
0x7 ADC sample lags by 157.5°
0x8 ADC sample lags by 180.0°
0x9 ADC sample lags by 202.5°
0xA ADC sample lags by 225.0°
0xB ADC sample lags by 247.5°
0xC ADC sample lags by 270.0°
0xD ADC sample lags by 292.5°
0xE ADC sample lags by 315.0°
0xF ADC sample lags by 337.5°
542
January 21, 2012
Texas Instruments-Production Data