TMS320VC5416_14 Datasheet, PDF (54/98 Pages) Texas Instruments – Fixed-Point Digital Signal Processor

TMS320VC5416
Fixed-Point Digital Signal Processor
SPRS095P – MARCH 1999 – REVISED OCTOBER 2008
www.ti.com
5.3 Electrical Characteristics
The electrical charactheristics are measured over recommended operating case temperature range (unless otherwise noted).
All values are typical unless otherwise specified.
PARAMETER
TEST CONDITIONS
MIN TYP MAX UNIT
V_OH
High-level output voltage⁽¹⁾
V_OL
Low-level output voltage⁽¹⁾
X2/CLKIN
DV_DD = 2.7 V to 3 V, I_OH = – 2 mA
DV_DD = 3 V to 3.6 V, I_OH = MAX
I_OL = MAX
2.2
2.4
– 40
V
0.4 V
40 µA
TRST, HPI16
With internal pulldown
– 10
800
HPIENA
With internal pulldown, RS = 0
I_I
Input current
(V_I = DV_SS to DV_DD)
TMS, TCK, TDI, HPI⁽²⁾ With internal pullups
A[17:0], D[15:0],
HD[7:0]
Bus holders enabled, DV_DD = MAX⁽³⁾
– 10
– 400
– 275
400
10 _µA
275
All other input-only pins
I_DDC
Supply current, core CPU
I_DDP
Supply current, pins
CV_DD = 1.6 V, f_x = 160 ,⁽⁴⁾T_C = 25°C
DV_DD = 3.0 V, f_x = 160 MHz,⁽⁴⁾T_C = 25°C
I_DD
Supply current,
standby
IDLE2
IDLE3 Divide-by-two
mode, CLKIN stopped
PLL × 1 mode, 20 MHz input
T_C = 25°C
T_C = 100°C
C_i
Input capacitance
C_o
Output capacitance
–5
60 ⁽⁵⁾
40 ⁽⁶⁾
2
1
30
5
5
5
mA
mA
mA
pF
pF
(1) All input and output voltage levels except RS, INT0-INT3, NMI, X2/CLKIN, CLKMD1-CLKMD3, BCLKRn, BCLKXn, HCS, HAS, HDS1,
HDS2, BIO, TCK, TRST, Dn, An, HDn are LVTTL-compatible.
(2) HPI input signals except for HPIENA and HPI16, when HPIENA = 0.
(3) V_IL(MIN) ≤ V_I ≤ V_IL(MAX) or V_IH(MIN) ≤ V_I ≤ V_IH(MAX)
(4) Clock mode: PLL × 1 with external source
(5) This value was obtained with 50% usage of MAC and 50% usage of NOP instructions. Actual operating current varies with program
being executed.
(6) This value was obtained with single-cycle external writes, CLKOFF = 0 and load = 15 pF. For more details on how this calculation is
performed, refer to the Calculation of TMS320LC54x Power Dissipation application report (literature number SPRA164).
5.3.1 Test Loading
Tester Pin Electronics
Data Sheet Timing Reference Point
42 W
4.0 pF
3.5 nH
1.85 pF
Transmission Line
Z0 = 50 W
(see note)
Output
Under
Test
Device Pin
(see note)
NOTE: The data sheet provides timing at the device pin. For output timing analysis, the tester pin electronics and its transmission line effects must
taken into account. A transmission line with a delay of 2 ns or longer can be used to produce the desired transmission line effect. The
transmission line is intended as a load only. It is not necessary to add or subtract the transmission line delay (2 ns or longer) from the data
sheet timings.
Input requirements in this data sheet are tested with an input slew rate of < 4 Volts per nanosecond (4 V/ns) at the device pin.
Figure 5-1. Tester Pin Electronics
54
Electrical Specifications
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