SM320C6201-EP Datasheet, PDF (54/59 Pages) Texas Instruments – FIXED-POINT DIGITAL SIGNAL PROCESSOR

SM320C6201-EP
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SGUS041A -- MAY 2003 -- REVISED JANUARY 2004
MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED)
CLKX
FSX
DX
DR
1
2
7
6
Bit 0
Bit 0
8
4
Bit(n-1)
Bit(n-1)
3
(n-2)
5
(n-2)
(n-3)
(n-3)
(n-4)
(n-4)
Figure 36. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1
timing requirements for McBSP as SPI master or slave: CLKSTP = 11b, CLKXP = 1^†‡ (see Figure 37)
--200
NO.
MASTER
SLAVE
MIN MAX
MIN MAX
4
t_su(DRV-CKXL)
Setup time, DR valid before CLKX low
12
5
t_h(CKXL-DRV)
Hold time, DR valid after CLKX low
4
† _{P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.}
‡ _{For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.}
2 -- 3P
5 + 6P
UNIT
ns
ns
switching characteristics over recommended operating conditions for McBSP as SPI master or
slave: CLKSTP = 11b, CLKXP = 1^†‡ (see Figure 37)
NO.
1
t_h(CKXH-FXL)
2
t_d(FXL-CKXL)
3
t_d(CKXH-DXV)
6
t_{dis(CKXH-DXHZ)}
PARAMETER
Hold time, FSX low after CLKX high^¶
Delay time, FSX low to CLKX low^#
Delay time, CLKX high to DX valid
Disable time, DX high impedance following last data bit from
CLKX high
--200
MASTER^§
SLAVE
MIN MAX
MIN MAX
H -- 2 H + 3
T -- 2 T + 1
--2
4 3P + 4 5P + 17
UNIT
ns
ns
ns
--2
4 3P + 3 5P + 17 ns
7
t_d(FXL-DXV)
Delay time, FSX low to DX valid
L -- 2 L + 4 2P + 2 4P + 17 ns
† _{P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.}
‡ _{For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.}
§ _{S = sample rate generator input clock = P if CLKSM = 1 (P = 1/CPU clock frequency)}
= sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period)
T = CLKX period = (1 + CLKGDV) * S
H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
¶ _{FSRP = FSXP = 1. As a SPI master, FSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on FSX}
and FSR is inverted before being used internally.
CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP
CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP
# _{FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock}
(CLKX).
54
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