DP83815_11 Datasheet, PDF (54/110 Pages) Texas Instruments – 10/100 Mb/s Integrated PCI Ethernet Media Access Controller and Physical Layer (MacPhyter)

4.0 Register Set (Continued)
Bit
Bit Name
Description
5-1
DRTH Rx Drain Threshold
Specifies the drain threshold in units of 8 bytes. When the number of bytes in the receive FIFO reaches
this value (times 8), or the FIFO contains a complete packet, the receive bus master state machine will
begin the transfer of data from the FIFO to host memory. Care must be taken when setting DRTH to a
value lower than the number of bytes needed to determine if packet should be accepted or rejected. In
this case, the packet might be rejected after the bus master operation to begin transferring the packet
into memory has begun. When this occurs, neither the OK bit or any error status bit in the descriptor’s
cmdsts will be set. A value of 0 is illegal, and the results are undefined.
This value is also used to compare with the accumulated packet length for early receive indication. When
the accumulated packet length meets or exceeds the DRTH value, the RXEARLY interrupt condition is
generated.
0
Reserved
4.2.13 CLKRUN Control/Status Register
This register mirrors the read/write control of the PMESTS and PMEEN from the PCI Configuration register PMCSR and
controls whether the chip is in the CLKRUNN or PMEN mode.
te ^{Tag: CCSR}
Offset: 003Ch
Size: 32 bits
Access: Read Write
Hard Reset: 00000000h
Soft Reset: unchanged
Bit
le 31-16
15
o _14-9
8
s _7-1
Ob ⁰
Bit Name
Description
reserved
(reads return 0)
PMESTS PME Status
Sticky bit which represents the state of the PME/CLKRUN logic, regardless of the state of the PMEEN bit.
Mirrored from PCI configuration register PMCSR. Writing a 1 to this bit clears it.
reserved
(reads return 0)
PMEEN PME Enable
When set to 1, this bit enables the assertion of the PMEN/CLKRUNN pin. When 0, the PMEN/CLKRUNN
pin is forced to be inactive. This value can be loaded from the EEPROM. Mirrored from PCI configuration
register PMCSR.
unused
(reads return 0)
CLKRUN_EN Clkrun Enable
When set to 1, this bit enables the CLKRUNN functionality of the PMEN/CLKRUNN pin. When 0, normal
PMEN functionality is active.
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