TPS549D22 Datasheet, PDF (53/63 Pages) Texas Instruments – 1.5-V to 16-V VIN, 4.5-V to 22-V VDD, 40-A SWIFT Synchronous Step-Down Converter with Full Differential Sense and PMBus

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TPS549D22
SLUSCI9 – AUGUST 2016
9 Power Supply Recommendations
This device is designed to operate from an input voltage supply between 1.5 V and 16 V. Ensure the supply is
well regulated. Proper bypassing of input supplies and internal regulators is also critical for noise performance,
as is the quality of the PCB layout and grounding scheme. See the recommendations in the Layout section.
10 Layout
10.1 Layout Guidelines
Consider these layout guidelines before starting a layout work using TPS549D22.
• It is absolutely critical that all GND pins, including AGND (pin 30), DRGND (pin 29), and PGND (pins 13, 14,
15, 16, 17, 18, 19, and 20) are connected directly to the thermal pad underneath the device via traces or
plane.
• Include as many thermal vias as possible to support a 40-A thermal operation. For example, a total of 35
thermal vias are used (outer diameter of 20 mil) in the available for purchase at ti.com.
• Placed the power components (including input/output capacitors, output inductor and device) on one side of
the PCB (solder side). Insert at least two inner layers (or planes) connected to the power ground, in order to
shield and isolate the small signal traces from noisy power lines.
• Place the VIN pin decoupling capacitors as close to the PVIN and PGND pins as possible to minimize the
input AC current loop. Place a high-frequency decoupling capacitor (with a value between 1 nF and 0.1 µF)
as close to the PVIN pin and PGND pin as the spacing rule allows. This placement helps suppress the switch
node ringing.
• Place VDD and BP decoupling capacitors as close to the device pins as possible. Do not use PVIN plane
connection for the VDD pin. Separate the VDD signal from the PVIN signal by using separate trace
connections. Provide GND vias for each decoupling capacitor and make the loop as small as possible.
• Ensure that the PCB trace defined as switch node (which connects the SW pins and up-stream of the output
inductor) are as short and wide as possible. In the EVM design, the SW trace width is 200 mil. Use a
separate via or trace to connect SW node to snubber and bootstrap capacitor. Do not combine these
connections.
• Place all sensitive analog traces and components (including VOSNS, RSP, RSN, ILIM, MODE, VSEL and
ADDR) far away from any high voltage switch node (itself and others), such as SW and BOOT to avoid noise
coupling. In addition, place MODE, VSEL and ADDR programming resistors near the device pins.
• The RSP and RSN pins operate as inputs to a differential remote sense amplifier that operates with very high
impedance. It is essential to route the RSP and RSN pins as a pair of diff-traces in Kelvin-sense fashion.
Route them directly to either the load sense points (+ and –) or the output bulk capacitors. The internal circuit
uses the VOSNS pin for on-time adjustment. It is critical to tie the VOSNS pin directly tied to VOUT (load
sense point) for accurate output voltage result.
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