TMS570LS20216_15 Datasheet, PDF (53/106 Pages) Texas Instruments – 16/32-BIT RISC Flash Microcontroller

Not Recommended For New Designs
TMS570LS20216, TMS570LS20206, TMS570LS10216
TMS570LS10206, TMS570LS10116, TMS570LS10106
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SPNS141F – AUGUST 2010 – REVISED JULY 2011
4.10 LPM
TMS570 Platform devices support multiple low power modes. These different modes allow the user to
trade-off the amount of current consumption during low power mode versus functionality and wake-up
time.
Supported Low Power modes on this devices are Doze, Snooze and Sleep; for detailed description please
refer to the Architecture section of the Technical Reference Manual.
4.11 Voltage Monitor
A voltage monitor has been implemented on this device. The purpose of this voltage monitor is to
eliminate the requirement for a specific sequence when powering up the core and I/O voltage supplies. It
also reduces the risk of corrupting memory or glitches on I/O pins during power-up, power-down or brown
outs. The voltage monitor does not eliminate the need of a voltage supervisor circuit to guarantee that the
device is held in reset when the voltage supplies are out of range. The voltage monitor thresholds can be
found in the Vmon section of the device electrical specifications.
When the voltage monitor detects a low voltage on the I/O supply, it will assert a reset. When the voltage
monitor detects a low voltage on the core supply, it asynchronously makes all output pins high impedance,
and asserts a reset. The voltage monitor is disabled when the device is in halt mode.
The voltage monitor has three filter functions:
• It rejects short low-going glitches on the PORRST pin
• It rejects noise on the VCCIO supply
• It rejects noise on the VCC supply
Please note that such glitches on VCC and VCCIO could still corrupt the system depending on many
factors. The width of noise that can be filtered by the voltage monitor on the VCC and VCCIO supplies is
shown in the table below. Glitches less than MIN will be filtered out, glitches greater than MAX are
guaranteed to generate a reset. The duration of glitches that will be filtered on the PORRST pin can be
found in Table 7-6, Timing Requirements for PORRST.
Table 4-13. VMON Supply Glitch Filter Capability
Parameter
Min
Max
Width of glitch on VCC that can be filtered out
300ns
1us
Width of glitch on VCCIO that can be filtered out
300ns
1us
4.12 CRC
MCRC Controller is a module which is used to perform CRC (Cyclic Redundancy Check) to verify the
integrity of memory system. A signature representing the contents of the memory is obtained when the
contents of the memory are read into MCRC Controller. The responsibility of MCRC controller is to
calculate the signature for a set of data and then compare the calculated signature value against a
pre-determined good signature value. MCRC controller provides up to four channels to perform CRC
calculation on multiple memories in parallel and can be used on any memory system. Channel 1 can also
be put into data trace mode. In data trace mode, MCRC controller compresses each data being read
through the CPU read data bus.
When using the MCRC module in PSA mode while ECC is enabled, bus masters (e.g. FTU, HTU, DMA or
CPU) should not write to the data RAM (TCRAM) to avoid corrupting the PSA value.
4.13 System Module Access
The system module access modes and access rights are shown in the following table.
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Peripherals
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