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TMS370C758B_12 Datasheet, PDF (53/75 Pages) Texas Instruments – 8-BIT MICROCONTROLLER | |||
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TMS370Cx5x
8-BIT MICROCONTROLLER
SPNS010F â DECEMBER 1986 â REVISED FEBRUARY 1997
Table 25. Peripheral File Frame Compilation (Continued)
ÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃ PF
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
ÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃ SPI MODULE CONTROL REGISTER
ÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃ P030
SPI SW
RESET
CLOCK
POLARITY
SPI BIT
RATE2
SPI BIT
RATE1
SPI BIT
RATE0
SPI
CHAR2
ÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃ P031
RECEIVER
OVERRUN
SPI INT
FLAG
â
â
â
MASTER/
SLAVE
ÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃ P032
to
ÃÃÃ ÃÃÃ P036
Reserved
ÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃ P037
RCVD7
RCVD6
RCVD5
RCVD4
RCVD3
RCVD2
ÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃ P038
Reserved
P039
SDAT7
SDAT6
SDAT5
SDAT4
SDAT3
SDAT2
ÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃ P03A
ÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃ to
ÃÃÃ ÃÃÃ P03C
Reserved
ÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃ P03D
â
â
â
â
SPICLK
DATA IN
SPICLK
DATA OUT
ÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃ P03E
SPISIMO
DATA IN
SPISIMO
SPISIMO
DATA OUT FUNCTION
SPISIMO
DATA DIR
SPISOMI
DATA IN
SPISOMI
DATA OUT
ÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃ P03F
SPI
STEST
SPI
PRIORITY
SPI
ESPEN
â
â
â
ÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃ TIMER 1 MODULE REGISTER
ÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃ Modes: Dual-Compare and Capture/Compare
ÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃ P040 Bit15
T1 Counter MSbyte
ÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃ P041 Bit7
T1 Counter LSbyte
ÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃ P042 Bit15
Compare Register MSbyte
P043 Bit 7
Compare Register LSbyte
ÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃ P044 Bit15
Capture/Compare Register MSbyte
ÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃ P045 Bit7
Capture/Compare Register LSbyte
ÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃ P046 Bit15
Watchdog Counter MSbyte
ÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃ P047 Bit7
Watchdog Counter LSbyte
ÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃ P048 Bit15
Watchdog Reset Key
ÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃ P049
WD OVRFL
TAP SELâ
WD
INPUT
SELECT2â
WD
INPUT
SELECT1â
WD
INPUT
SELECT0â
â
T1
INPUT
SELECT2
ÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃ P04A
WD OVRFL
RST ENAâ
WD OVRFL
INT ENA
WD OVRFL
INT FLAG
T1 OVRFL
INT ENA
T1 OVRFL
INT FLAG
â
ÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃ Mode: Dual-Compare
ÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃ P04B
T1EDGE
INT FLAG
T1C2
INT FLAG
T1C1
INT FLAG
â
â
T1EDGE
INT ENA
ÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃ P04C
T1
MODE = 0
T1C1
OUT ENA
T1C2
OUT ENA
T1C1
RST ENA
T1CR
OUT ENA
T1EDGE
POLARITY
ÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃ Mode: Capture/Compare
ÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃ P04B
T1EDGE
INT FLAG
â
T1C1
INT FLAG
â
â
T1EDGE
INT ENA
BIT 1
SPI
CHAR1
TALK
BIT 0
REG
SPI
CHAR0
SPI INT
ENA
SPICCR
SPICTL
RCVD1
SDAT1
RCVD0
SPIBUF
SDAT0
SPIDAT
SPICLK
FUNCTION
SPISOMI
FUNCTION
SPICLK
DATA DIR
SPIPC1
SPISOMI DATA
DIR
SPIPC2
â
â
SPIPRI
T1
INPUT
SELECT1
â
T1C2
INT ENA
T1CR
RST ENA
â
Bit 8 T1CNTR
Bit 0
Bit 8 T1C
Bit 0
Bit 8 T1CC
Bit 0
Bit 8 WDCNTR
Bit 0
Bit 0 WDRST
T1 INPUT
SELECT0
T1CTL1
T1 SW
RESET
T1CTL2
T1C1
INT ENA
T1EDGE
DET ENA
T1CTL3
T1CTL4
T1C1
INT ENA
T1CTL3
â Once the WD OVRFL RST ENA bit is set, these bits cannot be changed until a reset; this applies only to the standard
watchdog and to the simple counter. In the hard watchdog, these bits can be modified at any time; the WD INPUT SELECT2
bits are ignored.
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