CC113L_14 Datasheet, PDF (53/86 Pages) Texas Instruments – Value Line Receiver

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CC113L
SWRS108B – MAY 2011 – REVISED JUNE 2014
0x30
0x31
0x32
0x33
0x34
0x35
0x36
0x37
0x38
0x39
0x3A
0x3B
0x3C
0x3D
0x3E
0x3F
Table 5-19. SPI Address Space (continued)
Single Byte
+0x00
SRES
Reserved
SXOFF
SCAL
SRX
Reserved
SIDLE
Reserved
Reserved
SPWD
SFRX
Reserved
Reserved
SNOP
Reserved
Reserved
Write
Burst
+0x40
Single Byte
+0x80
SRES
Reserved
SXOFF
SCAL
SRX
Reserved
SIDLE
Reserved
Reserved
SPWD
SFRX
Reserved
Reserved
SNOP
Reserved
RX FIFO
Read
Burst
+0xC0
PARTNUM
VERSION
FREQEST
CRC_REG
RSSI
MARCSTATE
Reserved
Reserved
PKTSTATUS
Reserved
Reserved
RXBYTES
Reserved
Reserved
Reserved
RX FIFO
5.21.1 Configuration Register Details - Registers with preserved values in SLEEP state
Table 5-20. 0x00: IOCFG2 - GDO2 Output Pin Configuration
Bit
Field Name
Reset
R/W
Description
7
R0
Not used
6
GDO2_INV
0
R/W
Invert output, that is, select active low (1) / high (0)
5:0
GDO2_CFG[5:0]
41 (101001)
R/W
Default is CHP_RDYn (see Table 5-15).
Table 5-21. 0x01: IOCFG1 - GDO1 Output Pin Configuration
Bit
Field Name
Reset
R/W
Description
7
GDO_DS
0
R/W
Set high (1) or low (0) output drive strength on the GDO
pins.
6
GDO1_INV
0
R/W
Invert output, that is, select active low (1) / high (0)
5:0
GDO1_CFG[5:0]
46 (101110)
R/W
Default is 3-state (see Table 5-15).
Table 5-22. 0x02: IOCFG0 - GDO0 Output Pin Configuration
Bit
Field Name
7
6
GDO0_INV
5:0
GDO0_CFG[5:0]
Reset
0
0
63 (0x3F)
R/W
Description
R/W
Use setting from SmartRF Studio
R/W
Invert output, that is, select active low (1) / high (0)
Default is CLK_XOSC/192 (see Table 5-15).
R/W
It is recommended to disable the clock output in
initialization, in order to optimize RF performance.
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