TNETX4080 Datasheet, PDF (52/64 Pages) Texas Instruments – ThunderSWITCH IIE 8-PORT 10-/100-MBIT/S ETHERNETE SWITCH

TNETX4080
ThunderSWITCH II^™ 8-PORT 10-/100-MBIT/S ETHERNET^™ SWITCH
SPWS050A – AUGUST 1998 – REVISED NOVEMBER 1998
MII (ports 0–7)
Figures 11–13 show the timing for the eight MIIs operating at either 10-Mbit/s or 100-Mbit/s, and the GMII
operating at 100-Mbit/s.
Mxx_CRS and Mxx_COL are driven asynchronously by the PHY. Mxx_RXD3–Mxx_RXD0 is driven by the PHY
on the falling edge of Mxx_RCLK. Mxx_RXD3–Mxx_RXD0 timing must be met during clock periods in which
Mxx_RXDV is asserted. Mxx_RXDV is asserted and deasserted by the PHY on the falling edge of Mxx_RCLK.
Mxx_RXER is driven by the PHY on the falling edge of Mxx_RCLK.
MII receive (see Figure 11)
NO.
1 tsu(Mxx_RXD) Setup time, Mxx_RXD3–Mxx_RXD0 valid before Mxx_RCLK↑
1 tsu(Mxx_RXDV) Setup time, Mxx_RXDV valid before Mxx_RCLK↑
1 tsu(Mxx_RXER) Setup time, Mxx_RXER valid before Mxx_RCLK↑
2 th(Mxx_RXD) Hold time, Mxx_RXD3–Mxx_RXD0 valid after Mxx_RCLK↑
2 th(Mxx_RXDV) Hold time, Mxx_RXDV valid after Mxx_RCLK↑
2 th(Mxx_RXER) Hold time, Mxx_RXER valid after Mxx_RCLK↑
MIN MAX UNIT
8
ns
8
ns
8
ns
8
ns
8
ns
8
ns
1
2
Mxx_RCLK
Mxx_RXD3–Mxx_RXD0
Mxx_RXDV
Mxx_RXER
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
NOTE: For port 8, M08_RFCLK is used for the transmit clock input.
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Figure 11. MII Receive
Mxx_CRS and Mxx_COL are driven asynchronously by the PHY. Mxx_TXD3–Mxx_TXD0 is driven by the
reconciliation sublayer synchronous to Mxx_TCLK. Mxx_TXEN is asserted and deasserted by the reconciliation
sublayer synchronous to the Mxx_TCLK rising edge. Mxx_TXER is driven synchronous to the rising edge of
Mxx_TCLK.
52
• POST OFFICE BOX 655303 DALLAS, TEXAS 75265