PCF8523_12 Datasheet, PDF (52/75 Pages) NXP Semiconductors – Real-Time Clock (RTC) and calendar

NXP Semiconductors
PCF8523
Real-Time Clock (RTC) and calendar
12. Dynamic characteristics
Table 49. I²C-bus interface timing
All timing characteristics are valid within the operating supply voltage and ambient temperature range and reference to 30 %
and 70 % with an input voltage swing of V_SS to V_DD (see Figure 35).
Symbol Parameter
Conditions Standard mode Fast mode (FM) Fast mode plus (Fm+)^[1] Unit
Min Max Min
Max Min
Max
Pin SCL
f_SCL
SCL clock frequency
[2]
t_LOW LOW period of the SCL clock -
t_HIGH HIGH period of the SCL clock -
Pin SDA
-
100 -
400 -
1 000
kHz
4.7
-
1.3
- 0.5
-
s
4.0
-
0.6
- 0.26
-
s
t_SU;DAT data set-up time
t_HD;DAT data hold time
Pins SCL and SDA
-
250 -
100
- 50
-
ns
-
0
-
0
-0
-
ns
t_BUF
bus free time between a
-
4.7
-
1.3
- 0.5
-
s
STOP and START condition
t_SU;STO set-up time for STOP
-
4.0
-
0.6
- 0.26
-
s
condition
t_HD;STA hold time (repeated) START -
4.0
-
0.6
- 0.26
-
s
condition
t_SU;STA set-up time for a repeated
-
4.7
-
0.6
- 0.26
-
s
START condition
t_r
rise time of both SDA and
[3][4]
SCL signals
-
1000 20 + 0.1C_b 300 -
120
ns
t_f
fall time of both SDA and SCL ^[3][4]
signals
-
300 20 + 0.1C_b 300 -
120
ns
C_b
capacitive load for each bus
line
-
400 -
400 -
550
pF
t_VD;ACK data valid acknowledge time ^[5]
t_VD;DAT data valid time
[6]
t_SP
pulse width of spikes that
[7]
must be suppressed by the
input filter
-
3.45 -
-
3.45 -
-
50
-
0.9 -
0.9 -
50 -
0.45
s
0.45
s
50
ns
[1] Fast mode plus guaranteed at 3.0 V < V_DD < 5.5 V.
[2] The minimum SCL clock frequency is limited by the bus time-out feature, which resets the serial bus interface if either the SDA or SCL
is held LOW for a minimum of 25 ms. The bus time-out feature must be disabled for DC operation.
[3] A master device must internally provide a hold time of at least 300 ns for the SDA signal (refer to the V_IL of the SCL signal) in order to
bridge the undefined region of the falling edge of SCL.
[4] The maximum t_f for the SDA and SCL bus lines is 300 ns. The maximum fall time for the SDA output stage, t_f is 250 ns. This allows
series protection resistors to be connected between the SDA pin, the SCL pin and the SDA/SCL bus lines without exceeding the
maximum t_f.
[5] t_VD;ACK = time for acknowledgement signal from SCL LOW to SDA output LOW.
[6] t_VD;DAT = minimum time for valid SDA output following SCL LOW.
[7] Input filters on the SDA and SCL inputs suppress noise spikes of less than 50 ns.
PCF8523
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 5 July 2012
© NXP B.V. 2012. All rights reserved.
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