CR16MES5 Datasheet, PDF (52/101 Pages) National Semiconductor (TI) – Family of CompactRISC 16-Bit Microcontrollers

CR16MNS5, CR16MFS5, and CR16MPS5 are Obsolete Devices
Timer/Counter II (TnCNT1) counts down at the rate of the se-
lected clock. The TnB pin functions as the capture input. A
transition received on TnB transfers the timer contents to the
TnCRB register. The input pin can be configured to sense ei-
ther rising or falling edges.
The TnB input can be configured to preset the counter to
FFFF hex upon reception of a valid capture event. In this
case, the current value of the counter is transferred to the
capture register and then the counter is preset to FFFF hex.
The values captured in the TnCRB register at different times
reflect the elapsed time between transitions on the TnA pin.
The input signal on TnB must have a pulse width equal to or
greater than one system clock cycle.
There are two separate interrupts associated with the cap-
ture timer, each with its own enable bit and pending flag. The
two interrupt events are reception of a transition on TnB and
underflow of the TnCNT2 counter. The enable bits for these
events are TnBIEN and TnDIEN, respectively.
Reload A
TnAPND
TnCRA
Timer I
Clock
lete _{Timer II}
so ^Clock
Underflow
Timer/Counter I
TnCNT1
TnAIEN
TnATEN
TnBIEN
Capture B
TnCRB
Preset
TnBPND
Timer/Counter II
TnCNT2
TnBEN
TnDPND
TnDIEN
Figure 16. Mode 4: Input Capture Plus Timer Block Diagram
Timer
Interrupt I
TnA
Timer
Interrupt I
TnB
Timer
Interrupt II
Neither Timer/Counter I (TnCNT1) nor Timer/Counter II
(TnCNT2) can be configured to operate as an external event
b counter or to operate in the pulse accumulate mode because
the TnB input is used as a capture input. Attempting to select
one of these configurations will cause one or both counters
to stop. In this mode, Timer/Counter II must be enabled at all
O ^times.
rupts I and II are system interrupts T2A and T2B (IRQ11 and
IRQ10), respectively.
Table15 shows the events that trigger interrupts A, B, C, and
D in each of the four operating modes. Note that some inter-
rupt sources are not used in some operating modes, as indi-
cated by the notation “N/A” (Not Applicable) in the table.
14.3 TIMER INTERRUPTS
Each Multi-Function Timer unit has four interrupt sources,
designated A, B, C, and D. Interrupt sources A, B, and C are
mapped into a single system interrupt called Timer Interrupt
I, while interrupt source D is mapped into a system interrupt
called Timer Interrupt II. Each of the four interrupt sources
has its own enable bit and pending flag. The enable flags are
named TnAIEN, TnBIEN, TnCIEN, and TnDIEN. The pend-
ing flags are named TnAPND, TnBPND, TnCPND, and TnD-
PND.
For Multi-Function Timer unit MFT1, Timer Interrupts I and II
are system interrupts T1A and T1B (IRQ13 and IRQ12), re-
spectively. For Multi-Function Timer unit MFT2, Timer Inter-
14.4 TIMER I/O FUNCTIONS
Each Multi-Function Timer unit uses two I/O pins, called T1A
and T1B (for Timer MFT1) or T2A and T2B (for Timer MFT2).
The function of each pin depends on the timer operating
mode and the TnAEN and TnBEN enable bits. Table16
shows the functions of the pins in each operating mode, and
for each combination of enable bit settings.
When pin TnA is configured to operate as a PWM output
(TnAEN = 1), the state of the pin is toggled on each under-
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