ADS58C28 Datasheet, PDF (52/67 Pages) Texas Instruments – Dual Channel IF Receiver with SNRBoost3G

ADS58C28
SBAS509B – JUNE 2010 – REVISED OCTOBER 2010
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OFFSET CORRECTION
The ADS58C28 has an internal offset corretion algorithm that estimates and corrects dc offset up to ±10mV. The
correction can be enabled using the ENABLE OFFSET CORR serial register bit. Once enabled, the algorithm
estimates the channel offset and applies the correction every clock cycle. The time constant of the correction
loop is a function of the sampling clock frequency. The time constant can be controlled using the OFFSET CORR
TIME CONSTANT register bits, as described in Table 16.
Table 16. Time Constant of Offset Correction Algorithm
OFFSET CORR TIME CONSTANT
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
TIME CONSTANT, TC_CLK
(Number of Clock Cycles)
1M
2M
4M
8M
16M
32M
64M
128M
256M
512M
1024M
2048M
Reserved
Reserved
Reserved
Reserved
TIME CONSTANT, TC_CLK × 1/f_S (sec)⁽¹⁾
5ms
10ms
21ms
42ms
84ms
168ms
336ms
671ms
1.3s
2.7s
5.4s
10.7s
—
—
—
—
(1) Sampling frequency, f_S = 200MSPS.
After the offset is estimated, the correction can be frozen by setting FREEZE OFFSET CORR = 1. Once frozen,
the last estimated value is used for the offset correction of every clock cycle. Note that offset correction is
disabled by default after reset.
After a reset, the offset correction is disabled. To use offset correction:
• First, program the DIGITAL MODE 1 and DIGITAL MODE 2 bits (see Table 12) to enable the correction.
• Then set ENABLE OFFSET CORR to '1' and program the required time constant.
DIGITAL OUTPUT INFORMATION
The ADS58C28 provides 11-bit digital data for each channel and a common output clock synchronized with the
data.
Output Interface
Two output interface options are available: double data rate (DDR) LVDS and parallel CMOS. They can be
selected using the LVDS CMOS serial interface register bit .
DDR LVDS Outputs
In this mode, the data bits and clock are output using low-voltage differential signal (LVDS) levels. Two data bits
are multiplexed and output on each LVDS differential pair.
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