LM3S1608 Datasheet, PDF (508/632 Pages) Texas Instruments – ARM and Thumb are registered trademarks and Cortex is a trademark

Inter-Integrated Circuit (I²C) Interface
transmitter must then release SDA to allow the master to generate the STOP or a repeated START
condition.
14.3.1.5
Arbitration
A master may start a transfer only if the bus is idle. It's possible for two or more masters to generate
a START condition within minimum hold time of the START condition. In these situations, an
arbitration scheme takes place on the SDA line, while SCL is High. During arbitration, the first of
the competing master devices to place a '1' (High) on SDA while another master transmits a '0'
(Low) will switch off its data output stage and retire until the bus is idle again.
Arbitration can take place over several bits. Its first stage is a comparison of address bits, and if
both masters are trying to address the same device, arbitration continues on to the comparison of
data bits.
14.3.2
Available Speed Modes
The I²C clock rate is determined by the parameters: CLK_PRD, TIMER_PRD, SCL_LP, and SCL_HP.
where:
CLK_PRD is the system clock period
SCL_LP is the low phase of SCL (fixed at 6)
SCL_HP is the high phase of SCL (fixed at 4)
TIMER_PRD is the programmed value in the I²C Master Timer Period (I2CMTPR) register (see
page 526).
The I²C clock period is calculated as follows:
SCL_PERIOD = 2*(1 + TIMER_PRD)*(SCL_LP + SCL_HP)*CLK_PRD
For example:
CLK_PRD = 50 ns
TIMER_PRD = 2
SCL_LP=6
SCL_HP=4
yields a SCL frequency of:
1/T = 333 Khz
Table 14-3 on page 508 gives examples of timer period, system clock, and speed mode (Standard
or Fast).
Table 14-3. Examples of I²C Master Timer Period versus Speed Mode
System Clock
4 MHz
6 MHz
12.5 MHz
16.7 MHz
20 MHz
25 MHz
Timer Period
0x01
0x02
0x06
0x08
0x09
0x0C
Standard Mode
100 Kbps
100 Kbps
89 Kbps
93 Kbps
100 Kbps
96.2 Kbps
Timer Period
-
-
0x01
0x02
0x02
0x03
Fast Mode
-
-
312 Kbps
278 Kbps
333 Kbps
312 Kbps
508
June 19, 2012
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