TPS61021A Datasheet, PDF (5/33 Pages) Texas Instruments – TPS61021A 3-A Boost Converter with 0.5-V Ultra Low Input Voltage

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TPS61021A
SLVSDM0 – JUNE 2016
6.5 Electrical Characteristics
T_J = –40°C to 125°C, V_IN = 2.4 V and V_OUT = 3.3 V. Typical values are at T_J = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
POWER SUPPLY
V_IN
Input voltage range
0.5
4.4
V_{IN_UVLO} Under-voltage lockout threshold
V_IN rising
V_IN falling
0.8
0.9
0.28
0.4
0.5
IC enabled, No load, No switching
Quiescent current into VIN pin
V_IN = 1.8 V to 3.6 V, V_FB = V_REF +
I_Q
0.1 V, T_J up to 85°C
IC enabled, No load, No switching
Quiescent current into VOUT pin
V_OUT = 1.8 V to 4.0 V, V_FB = V_REF +
0.1 V, T_J up to 85°C
3.0
17
30
I_SD
Shutdown current into VIN and SW IC disabled, V_IN = 1.8 V to 3.6 V, T_J
pin
up to 85°C
0.5
3.0
OUTPUT
V_OUT
V_REF
Output voltage setting range
Reference voltage at the FB pin
PWM mode
PFM mode
1.8
4.0
775
795
815
801
V_OVP
Output over-voltage protection
threshold
V_OUT rising
4.15
4.35
4.60
V_{OVP_HYS}
I_{FB_LKG}
I_{SW_LKG}
I_{VOUT_LKG}
Over-voltage protection hysteresis
Leakage current at FB pin
Leakage current into SW pin
Leakage current into VOUT pin
IC disabled, T_J up to 85°C
IC disabled, V_OUT = 4.0 V, T_J up to
85°C
0.1
20
3.0
1
2
POWER SWITCH
R_DS(on)
High-side MOSFET on resistance
Low-side MOSFET on resistance
V_OUT = 3.3 V
V_OUT = 3.3 V
51
58
f_SW
Switching frequency
V_IN = 2.4 V, V_OUT = 3.3 V, PWM
mode
2.0
t_{OFF_min}
Minimum off time
I_{LIM_SW}
Valley current limit
LOGIC INTERFACE
V_IN = 2.4 V, V_OUT = 3.3 V
80
120
3.0
4.3
V_{EN_H}
EN Logic high threshold
V_{EN_L}
EN Logic Low threshold
PROTECTION
V_IN > 1.2 V
V_IN ≤ 1.2 V
V_IN > 1.2 V
V_IN ≤ 1.2 V
0.36
0.3 x VIN
0.84
0.7 x V_IN
T_SD
Thermal shutdown threshold
T_J rising
150
T_{SD_HYS} Thermal shutdown hysteresis
T_J falling below T_SD
20
UNIT
V
V
V
µA
µA
µA
V
mV
mV
V
V
nA
µA
µA
mΩ
mΩ
MHZ
ns
A
V
V
°C
°C
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