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TPS28225_15 Datasheet, PDF (5/38 Pages) Texas Instruments – TPS28225 High-Frequency 4-A Sink Synchronous MOSFET Drivers
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TPS28225
SLUS710D – MAY 2006 – REVISED SEPTEMBER 2015
6.4 Thermal Information
THERMAL METRIC
RθJA
RθJC(top)
RθJB
ψJT
ψJB
RθJC(bot)
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
TPS28225
VSON (DRB)
SOIC (D)
8 PINS
8 PINS
50.2
123.2
57.5
77.0
25.9
63.5
1.5
27.7
26.0
63.0
9.5
N/A
UNIT
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
6.5 Electrical Characteristics(1)
VDD = 7.2 V, EN/PG pulled up to VDD by 100-kΩ resistor, TA = TJ = –40°C to 125°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNDER VOLTAGE LOCKOUT
Rising threshold
Falling threshold
Hysteresis
VPWM = 0 V
VPWM = 0 V
3.2
3.5
3.8
2.7
3.0
0.5
BIAS CURRENTS
IDD(off)
Bias supply current
VEN/PG = low, PWM pin floating
350
IDD
Bias supply current
VEN/PG = high, PWM pin floating
500
INPUT (PWM)
IPWM
Input current
PWM 3-state rising threshold(2)
VPWM = 5 V
VPWM = 0 V
185
–200
1.0
tHLD_R
TMIN
PWM 3-state falling threshold
3-state shutdown Hold-off time
VPWM PEAK = 5 V
PWM minimum pulse to force UGATE
pulse
CL = 3 nF at UGATE , VPWM = 5 V
3.4
3.8
4.0
250
30
ENABLE/POWER GOOD (EN/PG)
Enable high rising threshold
PG FET OFF
1.7
2.1
Enable low falling threshold
PG FET OFF
0.8
1.0
Hysteresis
0.35
0.70
Power good output
VDD = 2.5 V
0.2
UPPER GATE DRIVER OUTPUT (UGATE)
Source resistance
Source current (2)
tRU
Rise time
Sink resistance
Sink current (2)
tFU
Fall time
500 mA source current
VUGATE-PHASE = 2.5 V
CL = 3 nF
500 mA sink current
VUGATE-PHASE = 2.5 V
CL = 3 nF
1.0
2.0
2.0
10
1.0
2.0
2.0
10
(1) Typical values for TA = 25°C
(2) Not production tested.
UNIT
V
V
V
μA
μA
μA
μA
V
V
ns
ns
V
V
V
V
Ω
A
ns
Ω
A
ns
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