TMP103 Datasheet, PDF (5/30 Pages) Texas Instruments – Low-Power, Digital Temperature Sensor with Two-Wire Interface in WCSP

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TMP103
SBOS545B – FEBRUARY 2011 – REVISED JANUARY 2016
6.6 Timing Requirements
See ⁽¹⁾
f_(SCL)
f_(SCL)
t_(BUF)
t_(HDSTA)
t_(SUSTA)
t_(SUSTO)
t_(HDDAT)
t_(SUDAT)
t_(LOW)
t_(LOW)
t_(HIGH)
t_F
t_R
t_R
SCL operating frequency, V_S > 1.7 V
SCL operating frequency, V_S < 1.7 V
Bus free time between STOP and START condition
Hold time after repeated START condition.
After this period, the first clock is generated.
Repeated START condition setup time
STOP condition setup Time
Data hold time
Data setup time
SCL clock low period, V_S > 1.7 V
SCL clock low period, V_S < 1.7 V
SCL clock high period
Clock/data fall time
Clock/data rise time
Clock/data rise time for SCLK ≤ 100 kHz
FAST MODE
MIN
MAX
0.001
0.4
0.001
0.4
600
100
100
100
20
100
1300
1300
600
400
300
300
1000
HIGH-SPEED MODE
MIN
MAX
0.001
3.4
0.001
2.75
160
100
100
100
10
125
10
160
200
60
160
UNIT
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
(1) Values based on a statistical analysis of a one-time sample of devices. Minimum and maximum values are not guaranteed and not
production tested.
The TMP103 is two-wire and SMBus compatible. Figure 1 to Figure 5 describe the various operations on the
TMP103. Parameters for Figure 1 are defined in Timing Requirements. Bus definitions are:
Bus Idle: Both SDA and SCL lines remain high.
Start Data Transfer: A change in the state of the SDA line, from high to low, while the SCL line is high, defines
a START condition. Each data transfer is initiated with a START condition.
Stop Data Transfer: A change in the state of the SDA line from low to high while the SCL line is high defines a
STOP condition. Each data transfer is terminated with a repeated START or STOP condition.
Data Transfer: The number of data bytes transferred between a START and a STOP condition is not limited and
is determined by the master device.
Acknowledge: Each receiving device, when addressed, is obliged to generate an Acknowledge bit. A device
that acknowledges must pull down the SDA line during the Acknowledge clock pulse in such a way that the SDA
line is stable low during the high period of the Acknowledge clock pulse. Setup and hold times must be taken into
account. On a master receive, the termination of the data transfer can be signaled by the master generating a
Not-Acknowledge (1) on the last byte transmitted by the slave.
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