TM4C123FH6PM Datasheet, PDF (5/1371 Pages) Texas Instruments – Tiva™ TM4C123FH6PM Microcontroller

Tiva^™ TM4C123FH6PM Microcontroller
5.2.6
5.3
5.4
5.5
5.6
System Control ........................................................................................................... 225
Initialization and Configuration ..................................................................................... 229
Register Map .............................................................................................................. 229
System Control Register Descriptions ........................................................................... 234
System Control Legacy Register Descriptions ............................................................... 414
6
System Exception Module ................................................................................... 476
6.1 Functional Description ................................................................................................. 476
6.2 Register Map .............................................................................................................. 476
6.3 Register Descriptions .................................................................................................. 476
7
7.1
7.2
7.2.1
7.2.2
7.2.3
7.2.4
7.3
7.4
7.5
7.6
Internal Memory ................................................................................................... 484
Block Diagram ............................................................................................................ 484
Functional Description ................................................................................................. 485
SRAM ........................................................................................................................ 485
ROM .......................................................................................................................... 486
Flash Memory ............................................................................................................. 488
EEPROM .................................................................................................................... 494
Register Map .............................................................................................................. 500
Flash Memory Register Descriptions (Flash Control Offset) ............................................ 501
EEPROM Register Descriptions (EEPROM Offset) ........................................................ 519
Memory Register Descriptions (System Control Offset) .................................................. 536
8
Micro Direct Memory Access (μDMA) ................................................................ 545
8.1 Block Diagram ............................................................................................................ 546
8.2 Functional Description ................................................................................................. 546
8.2.1 Channel Assignments .................................................................................................. 547
8.2.2 Priority ........................................................................................................................ 548
8.2.3 Arbitration Size ............................................................................................................ 548
8.2.4 Request Types ............................................................................................................ 548
8.2.5 Channel Configuration ................................................................................................. 549
8.2.6 Transfer Modes ........................................................................................................... 551
8.2.7 Transfer Size and Increment ........................................................................................ 559
8.2.8 Peripheral Interface ..................................................................................................... 559
8.2.9 Software Request ........................................................................................................ 559
8.2.10 Interrupts and Errors .................................................................................................... 560
8.3 Initialization and Configuration ..................................................................................... 560
8.3.1 Module Initialization ..................................................................................................... 560
8.3.2 Configuring a Memory-to-Memory Transfer ................................................................... 561
8.3.3 Configuring a Peripheral for Simple Transmit ................................................................ 562
8.3.4 Configuring a Peripheral for Ping-Pong Receive ............................................................ 564
8.3.5 Configuring Channel Assignments ................................................................................ 566
8.4 Register Map .............................................................................................................. 566
8.5 μDMA Channel Control Structure ................................................................................. 568
8.6 μDMA Register Descriptions ........................................................................................ 575
9
9.1
9.2
9.2.1
9.2.2
General-Purpose Input/Outputs (GPIOs) ........................................................... 609
Signal Description ....................................................................................................... 609
Functional Description ................................................................................................. 612
Data Control ............................................................................................................... 613
Interrupt Control .......................................................................................................... 614
June 12, 2014
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