TLC32071 Datasheet, PDF (5/15 Pages) Texas Instruments – HIGH-SPEED 8-BIT A/D AND D/A CONVERTER WITH 8-CHANNEL MULTIPLEXER

TLC32071
HIGHĆSPEED 8ĆBIT A/D AND D/A CONVERTER
WITH 8ĆCHANNEL MULTIPLEXER
SLAS051−D3973, DECEMBER 1991
PRINCIPLES OF OPERATION
writing control words to the TLC32071
With the CSCNTRL input low, a control word is written to the TLC32071 by placing data on the D7−D0 inputs
and applying a low-going pulse to the write enable input (WE). Data is latched on the rising edge of the WE pulse.
The values of D0 and D1 of the control word determine whether the data is latched in the range/ADC MUX control
register or the REF MUX register. See Tables 1, 2, 3, and 4 for data-bit formats.
operation of the ADC channel
Analog-to-digital conversion begins when gain-select and channel-select data word is latched in the range/ADC
MUX control register by the rising edge of the WE pulse. This data word controls the state of the range/ADC
input multiplexer. After the conversion time, the conversion result may be read by taking the DEN input low while
the CSAN input is low. Writing of data to the REF MUX control register (using CSCNTRL and WE with D0 and
D1 both 0) does not start a conversion. Each time one of the A0 through A5 signal channels is selected, the first
conversion result after selection should be ignored due to internal input amplifier settling time. If this channel
remains selected, subsequent conversions are valid.
operation of the DAC channel
When the CSAN input is low, digital-to-analog conversion is performed by placing input data on data bus
DB7−DB0 and applying a low-going pulse to WE. The data word is latched on the rising edge of the WE pulse
and is decoded to an equivalent analog voltage. The conversion occurs internally in approximately 100 ns with
the D/A conversion result available at the ANAOUT output after a specified settling time.
digital loopback mode
Digital loopback enables the simultaneous testing of the A/D and D/A channels. When digital loopback is
enabled, the A/D conversion result is transferred to the D/A input latches on the next rising edge of DEN. The
analog signal from the input pin at the A/D converter is transferred through the D/A converter to the analog output
ANAOUT. To enable digital loopback, write to the REF MUX control register (see data word format in Table 3)
to set bit D6. Then, perform A/D conversion (as in normal operation) by writing channel select and range select
information to the range/ADC MUX control register. This is done by strobing WE while CSCTRL is low. Read
the conversion result by strobing DEN while holding CSAN low when digital loopback is enabled. The A/D
conversion result is transferred to the DAC on the rising edge of DEN (See Tables 1, 2, 3, and 4).
reset operation
CSAN and CSCNTRL should be held high during a reset operation. When the RESET input is taken low, the
internal reset signal clears the range/ADC MUX control register, the REF MUX control register, and the DAC
input register. The following conditions exist after reset:
1. The DAC output is set to the voltage at the ANLG COM input.
2. The DAC range is set to ANLG COM ±4 V.
3. The A0 analog channel is selected and the A0 and A1 amplifier ranges are set to ANLG COM ±4 V.
4. The 2.5 V reference is selected at the REF output.
5. Digital loopback is disabled.
analog inputs
The ANLG COM voltage establishes the operating midpoint of the input amplifiers, A0 through A5. When the
input signal voltage equals this voltage, the ADC output is ideally digital count zero. These amplifiers level shift
to the ADC midpoint of 2.5 V and scale the input voltage range to the ADC range of 0.5 to 4.5 V. The A6 and
A7 noninverting inputs are centered at the 2.5 V internally generated voltage reference and are connected
directly to the input MUX. Table 5 gives the full scale input range and the midpoint voltages applicable for the
individual analog inputs.
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