SN74LVC1G34_16 Datasheet, PDF (5/38 Pages) Texas Instruments – SN74LVC1G34 Single Buffer Gate

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SN74LVC1G34
SCES519M – DECEMBER 2003 – REVISED APRIL 2016
7 Specifications
7.1 Absolute Maximum Ratings⁽¹⁾
over operating free-air temperature range (unless otherwise noted)
V_CC
Supply voltage range
V_I
Input voltage range
V_O
Voltage range applied to any output in the high-impedance or power-off state⁽²⁾
V_O
Voltage range applied to any output in the high or low state⁽²⁾⁽³⁾
I_IK
Input clamp current
V_I < 0
I_OK
Output clamp current
V_O < 0
I_O
Continuous output current
Continuous current through V_CC or GND
T_stg
Storage temperature range
T_J
Max Junction temperature
MIN
MAX
–0.5
6.5
–0.5
6.5
–0.5
6.5
–0.5 V_CC + 0.5
–50
–50
±50
±100
-65
150
150
UNIT
V
V
V
V
mA
mA
mA
mA
°C
°C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
(3) The value of V_CC is provided in the Recommended Operating Conditions table.
7.2 ESD Ratings
MIN
V_(ESD)
Electrostatic discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all
pins ⁽¹⁾
Charged device model (CDM), per JEDEC specification
JESD22-C101, all pins⁽²⁾
MAX
±2
±1
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
UNIT
kV
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