SN65HVS883 Datasheet, PDF (5/28 Pages) Texas Instruments – 24 V, Eight-Channel Digital-Input Serializer

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6.5 Electrical Characteristics
all voltages measured against FGND unless otherwise stated, see Figure 12
SYMBOL
PARAMETER
PIN
TEST CONDITIONS
V_TH–(IP)
V_TH+(IP)
V_HYS(IP)
V_TH–(IN)
V_TH+(IN)
V_HYS(IN)
V_{TH–(V24)}
V_TH+(V24)
V_HYS(V24)
Low-level device input threshold voltage
High-level device input threshold voltage
Device input hysteresis
Low-level field input threshold voltage
High-level field input threshold voltage
Field input hysteresis
Low-level V24-monitor threshold voltage
High-level V24-monitor threshold voltage
V24-monitor hysteresis
R_IP
Input resistance
I_IP-LIM
V_OL
V_OH
I_IL
Input current limit
Logic low-level output voltage
Logic high-level output voltage
Logic input leakage current
IP0–IP7
18 V< V24 < 34 V,
R_IN = 0 Ω ,
R_LIM = 25 kΩ
measured at
field side of R_IN
18 V < V24 < 34 V,
R_IN = 1.2 kΩ ± 5%,
R_LIM = 25 kΩ
V24
IP0–IP7
SOP, CHOK
DB0, DB1, SIP,
LD, CE, CLK
3 V < V_IPx < 6 V,
R_IN = 1.2 kΩ ± 5%,
R_LIM = 25 kΩ
10 V < V_IPx < 34 V,
R_LIM = 25 kΩ
I_OL = 20 μA
I_OH = –20 μA
I_RE-on
RE on-state current
I_CC(V24) Supply current
RE0–RE7
V24
R_LIM = 25 kΩ,
RE_X = FGND
IP0 to IP7 = V24,
5VOP = open,
RE_X = FGND,
All logic inputs open
V_O(5V)
Linear regulator output voltage
I_LIM(5V) Linear regulator output current limit
ΔV₅/ΔV₂₄ Line regulation
5VOP
5VOP, V24
18 V < V24 < 34 V,
no load
18 V < V24 < 34 V,
I_L = 50 mA
18 V < V24 < 34 V,
I_L = 5 mA
DB0 = open,
DB1 = FGND
t_DB
Debounce times of input channels
IP0–IP7
DB0 = FGND,
DB1 = open
DB0 = DB1 = open
t_DB-HL
t_DB-LH
Voltage monitor debounce time after V24 < 15
V (CHOK turns low)
Voltage monitor debounce time after V24 > 18
V (CHOK turns high)
V24, CHOK
T_SHDN Shutdown temperature
SN65HVS883
SLASEE6 – SEPTEMBER 2016
MIN TYP
4 4.3
5.2
0.9
6 8.4
9.4
1
15 16.05
16.8
0.75
MAX
5.5
10
18
UNIT
V
V
V
V
V
V
V
V
V
1.4 1.83 2.3 kΩ
3.15 3.6
4
–50
2.8 3.15
4 mA
0.4 V
V
50 μA
3.5 mA
8.7 mA
4.5
5
4.5
5
115
0
1
3
1
6
170
5.5
V
5.5
mA
2 mV/V
ms
ms
ms
°C
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