 English |
|
|
|
|
|
|
|
| LM5050MKX-2 Datasheet, PDF (5/22 Pages) Texas Instruments – LM5050-2 High Side OR-ing FET Controller | |||
| |||
| ◁ |
LM5050-2
www.ti.com
SNVS679B â NOVEMBER 2010 â REVISED MARCH 2013
Electrical Characteristics (continued)
Limits in standard type are for TJ = 25°C only; limits in boldface type apply over the operating junction temperature (TJ)
range of -40°C to +125°C. Minimum and Maximum limits are specified through test, design, or statistical correlation. Typical
values represent the most likely parametric norm at TJ = 25°C, and are provided for reference purposes only. Unless
otherwise stated the following conditions apply: VIN = 12.0V, VOUT = 12.0V, VOFF= 0.0V, CGATE= 47 nF, and TJ = 25°C.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
OFF Pin
VOFF(IH)
VOFF(IL)
ÎVOFF
IOFF
nFGD Pin
OFF Input High Threshold Voltage
OFF Input Low Threshold Voltage
OFF Threshold Voltage Hysteresis
OFF Pin Internal Pull-down
VOUT = VIN-500 mV
VOFF Rising
VOUT = VIN - 500 mV
VOFF Falling
VOFF(IH) - VOFF(IL)
VOFF = 5.0V
-
1.55
1.73
V
1.09
1.41
-
-
160
-
mV
2.0
5
8.0
µA
VSD(TST)
ÎVSD(TST)
nFGDVOL
nFGDIOL
FET Test Threshold Voltage
VIN < VOUT
FET Test Threshold Voltage Hysteresis
VOFF = 5V
VOUT = 12V
VIN falling from 12V
nFGD Output Low Voltage
nFGD Output = On
nFGD Output Leakage Current
nFGD Output = Off
VOFF = 5V
InFGD = 1 mA Sinking
VOFF = 0V
VnFGD = 5.5V
250
350
450
mV
-
95
-
mV
-
630
850
mV
-
0.001
0.7
µA
200 mV
VSD(REG)
0 mV
VSD(REV)
-500 mV
VGATE
VIN > VOUT
VIN < VOUT
tGATE(OFF)
1.0V
0.0V
Figure 4. Gate Off Timing for Forward to Reverse Transition
Copyright © 2010â2013, Texas Instruments Incorporated
Product Folder Links: LM5050-2
Submit Documentation Feedback
5
|
▷ |
German
Russian
Spanish
Italian
Polish
Chinese
Japanese
Korean
French
Portuguese