HD3SS213ZQER Datasheet, PDF (5/14 Pages) Texas Instruments – 5.4Gbps DisplayPort 1.2a 2:1/1:2 Differential Switch

HD3SS213
www.ti.com
SLAS901A – SEPTEMBER 2013 – REVISED SEPTEMBER 2013
FUNCTIONAL DESCRIPTION
Refer to Figure 2.
The HD3SS213 behaves as a two to one or one to two using high bandwidth pass gates. The input ports are
selected using the AUX_SEL and Dx_SEL pins which are shown in Table 1.
Table 1. AUX/DDC Switch Control Logic
CONTROL LINES⁽¹⁾
AUX_SEL Dx_SEL
L
L
L
H
H
L
H
H
M
L
M
H
AUXA
To/From AUXC
Z
Z
Z
To/From AUXC
Z
AUXB
Z
To/From AUXC
Z
Z
Z
To/From AUXC
SWITCHED I/O PINS⁽²⁾
AUXC
DDCA
To/From AUXA
Z
To/From AUXB
Z
To/From DDCA
To/From AUXC
To/From DDCB
Z
To/From AUXA
To/From DDCC
To/From AUXB
Z
DDCB
Z
Z
Z
To/From AUXC
Z
To/From DDCC
(1) The ports which are not selected by the control lines will be in high impedance status.
(2) OE pin - For normal operation, drive OE high. Driving the OE pin low will disable the switch.
DDCC
Z
Z
Z
Z
To/From DDCA
To/From DDCB
ABSOLUTE MAXIMUM RATINGS⁽¹⁾⁽²⁾
over operating free-air temperature range (unless otherwise noted)
Supply voltage range⁽³⁾
Voltage range
Electrostatic discharge
V_DD
Differential I/O
Control pin
Human body model⁽⁴⁾
Charged-device model⁽⁵⁾
Operating free-air temperature
Continuous power dissipation
VALUE
MIN
MAX
UNIT
–0.5
4
V
–0.5
4
V
–0.5
V_DD + 0.5
±2000
V
±500
V
–40
105
°C
See Thermal Table
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any conditions beyond those indicated under recommended operating conditions
is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values, except differential voltages, are with respect to network ground terminal.
(3) Tested in accordance with JEDEC Standard 22, Test Method A114-B
(4) Tested in accordance with JEDEC Standard 22, Test Method C101-A
(5) Tested in accordance with JEDEC Standard 22, Test Method A115-A
THERMAL INFORMATION
θ_JA
θ_JCtop
θ_JB
ψ_JT
ψ_JB
THERMAL METRIC⁽¹⁾
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
Junction-to-top characterization parameter
Junction-to-board characterization parameter
HD3SS213
HIGH-K BOARD
90.5
41.9
53.9
1.8
53.4
UNITS
°C/W
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
Copyright © 2013, Texas Instruments Incorporated
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