DS90C363B Datasheet, PDF (5/17 Pages) National Semiconductor (TI) – +3.3V Programmable LVDS Transmitter 18-Bit Flat Panel Display (FPD) Link -65 MHz

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AC Timing Diagrams
DS90C363B
SNLS179F – APRIL 2004 – REVISED APRIL 2013
Figure 2. “Worst Case” Test Pattern
A. The worst case test pattern produces a maximum toggling of digital circuits, LVDS I/O and CMOS/TTL I/O.
B. The 16 grayscale test pattern tests device power consumption for a “typical” LCD display pattern. The test pattern
approximates signal switching needed to produce groups of 16 vertical stripes across the display.
C. Figure 2 and Figure 3 show a falling edge data strobe (TxCLK IN/RxCLK OUT).
D. Recommended pin to signal mapping. Customer may choose to define differently.
Figure 3. “16 Grayscale” Test Pattern
Figure 4. DS90C363B (Transmitter) LVDS Output Load
Figure 5. DS90C363B (Transmitter) LVDS Transition Times
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