DS1651_11 Datasheet, PDF (5/12 Pages) Texas Instruments – Quad High Speed MOS Sense Amplifiers

Switching Characteristics
V_CC = 5 V_DC, V_EE = −5 V_DC, T_A = 25˚C unless otherwise noted.
Symbol
Parameter
t_PHL(D)
High-to-Low Logic Level Propagation
Delay Time (Differential Inputs)
t_PLH(D)
Low-to-High Logic Level Propagation
Delay Time (Differential Inputs)
t_POH(S)
TRI-STATE to High Logic Level
Propagation Delay Time (Strobe)
t_PHO(S)
High Logic Level to TRI-STATE
Propagation Delay Time (Strobe)
t_POL(S)
TRI-STATE to Low Logic Level
Propagation Delay Time (Strobe)
t_PLO(S)
Low Logic Level to TRI-STATE
Propagation Delay Time (Strobe)
Conditions
5 mV + V_IS,
(Figure 2)
DS1651/
DS3651
5 mV + V_IS,
(Figure 2)
DS1651/
DS3651
(Figure 1)
DS1651/
DS3651
(Figure 1)
DS1651/
DS3651
(Figure 1)
DS1651/
DS3651
(Figure 1)
DS1651/
DS3651
Min Typ Max Units
23
45
ns
22
55
ns
16
21
ns
7
18
ns
19
27
ns
14
29
ns
Note 1: Derate cavity package 10.1 mW/˚C above 25˚C; derate molded package 11.8 mW/˚C above 25˚C.
Note 2: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. Except for “Operating Temperature Range” they
are not meant to imply that the device should be operated at these limits. The table of “Electrical Characteristics” provides conditions for actual device operation.
Note 3: Unless otherwise specified min/max limits apply across the 0˚C to +70˚C range for the DS3651 and across the −55˚C to +125˚C range for the DS1651. All
typical values are for T_A = 25˚C, V_CC = 5V and V_EE = −5V.
Note 4: All currents into device pins shown as positive, out of device pins as negative, all voltages referenced to ground unless otherwise noted. All values shown
as max or min on absolute value basis.
Note 5: Only one output at a time should be shorted.
Note 6: A parameter which is of primary concern when designing with sense amplifiers is, what is the minimum differential input voltage required at the sense am-
plifier input terminals to guarantee a given output logic state. This parameter is commonly referred to as threshold voltage. It is well known that design considerations
of threshold voltage are plagued by input offset currents, bias currents, network source resistances, and voltage gain. As a design convenience, the DS1651 and
DS3651 are specified to a parameter called input sensitivity (V_IS). This parameter takes into consideration input offset currents and bias currents, and guarantees
a minimum input differential voltage to cause a given output logic state with respect to a maximum source impedance of 200Ω at each input.
Switching Time Waveform
Note: Output of channel B shown under test, other channels are tested similarly.
Delay
V1
V2
t_PLO(S))
t_POL(S)
t_PHO(S)
t_POH(S)
100 mV
100 mV
GND
GND
GND
GND
100 mV
100 mV
C_L includes jig and probe capacitance.
E_IN waveform characteristics: t_TLH and t_THL ≤ 10 ns measured 10% to 90%
PRR = 1 MHz
Duty cycle = 50%
S1
Closed
Closed
Closed
Open
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DS007528-3
S2
Closed
Open
Closed
Closed
C_L
15 pF
50 pF
15 pF
50 pF