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| DAC8571IDGKRG4 Datasheet, PDF (5/31 Pages) Texas Instruments – 16-BIT, LOW POWER, VOLTAGE OUTPUT | |||
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DAC8571
www.ti.com
SLAS373A â DECEMBER 2002 â REVISED JULY 2003
TIMING CHARACTERISTICS (continued)
VDD = +2.7 V to +5.5 V; RL = 2 k⦠to GND; all specifications -40°C to 105°C (unless otherwise noted)
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
TYP
tRCL1
tFCL
tRCA
tFDA
Rise time of SCL signal after a
repeated START condition, and
after an acknowledge BIT
Fall time of SCL signal
Rise time of SDA signal
Fall time of SDA signal
Standard mode
Fast mode
High-speed mode, CB - 100pF max
High-speed mode, CB - 400pF max
Standard mode
Fast mode
High-speed mode, CB - 100pF max
High-speed mode, CB - 400pF max
Standard mode
Fast mode
High-speed mode, CB - 100pF max
High-speed mode, CB - 400pF max
Standard mode
Fast mode
High-speed mode, CB - 100pF max
High-speed mode, CB - 400pF max
Standard mode
20 + 0.1CB
20 + 0.1CB
10
20
20 + 0.1CB
20 + 0.1CB
10
20
20 + 0.1CB
20 + 0.1CB
10
20
20 + 0.1CB
20 + 0.1CB
10
20
4.0
tSU; tSTO
Setup time for STOP condition
Fast mode
600
High-speed mode
160
CB
Capacitive load for SDA and SCL
tSP
Pulse width of spike suppressed
Fast mode
High-speed mode
Noise margin at the HIGH level for
VNH
each connected device (including
hysteresis)
Standard mode
Fast mode
High-speed mode
0.2VDO
Noise margin at the LOW level for
VNL
each connected device (including
hysteresis)
Standard mode
Fast mode
High-speed mode
0.1VDO
MAX
1000
300
80
1600
300
300
40
80
1000
300
80
160
300
300
80
160
400
50
10
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
ns
ns
pF
ns
ns
V
V
5
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