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| DAC7558_16 Datasheet, PDF (5/31 Pages) Texas Instruments – 12-BIT, OCTAL, ULTRALOW GLITCH, VOLTAGE OUTPUT DIGITAL-TO-ANALOG CONVERTER | |||
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DAC7558
www.ti.com
SLAS435A â MAY 2005 â REVISED DECEMBER 2005
TIMING CHARACTERISTICS(1)(2)
VDD = 2.7 V to 5.5 V, RL = 2 k⦠to GND; all specifications â40°C to 105°C, unless otherwise specified
PARAMETER
TEST CONDITIONS
MIN
TYP
t1(3) SCLK cycle time
VDD = 2.7 V to 3.6 V
20
VDD = 3.6 V to 5.5 V
20
t2
SCLK HIGH time
VDD = 2.7 V to 3.6 V
10
VDD = 3.6 V to 5.5 V
10
t3
SCLK LOW time
VDD = 2.7 V to 3.6 V
10
VDD = 3.6 V to 5.5 V
10
t4
SYNC falling edge to SCLK falling edge setup
time
VDD = 2.7 V to 3.6 V
VDD = 3.6 V to 5.5 V
4
4
t5
Data setup time
VDD = 2.7 V to 3.6 V
5
VDD = 3.6 V to 5.5 V
5
t6
Data hold time
VDD = 2.7 V to 3.6 V
4.5
VDD = 3.6 V to 5.5 V
4.5
t7
SCLK falling edge to SYNC rising edge
VDD = 2.7 V to 3.6 V
VDD = 3.6 V to 5.5 V
0
0
t8
Minimum SYNC HIGH time
VDD = 2.7 V to 3.6 V
20
VDD = 3.6 V to 5.5 V
20
t9
SCLK falling edge to SDO valid
VDD = 2.7 V to 3.6 V
VDD = 3.6 V to 5.5 V
10
10
t10
CLR pulse width low
VDD = 2.7 V to 3.6 V
10
VDD = 3.6 V to 5.5 V
10
MAX UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
(1) All input signals are specified with tR = tF = 1 ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2.
(2) See Serial Write Operation timing diagram Figure 1.
(3) Maximum SCLK frequency is 50 MHz at VDD = 2.7 V to 5.5 V.
t1
SCLK
t8
t4
t3
t2
t7
SYNC
t5
t6
SDIN
D23 D22 D21 D20 D19
D1 D0 D23
D0
SDO
Input Word n
t9 Input Word n+1
D23
D22
D0
CLR
Undefined
t10
Input Word n
Figure 1. Serial Write Operation
5
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