DAC5311 Datasheet, PDF (5/43 Pages) Texas Instruments – 1.8V to 5.5V, 80mA, 8-, 10-, and 12-Bit, Low-Power, Single-Channel,

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PIN CONFIGURATION
DCK PACKAGE
SC70-6
(TOP VIEW)
DAC5311
DAC6311
DAC7311
SBAS442A – AUGUST 2008 – REVISED AUGUST 2011
SYNC 1
SCLK 2
D_IN 3
6 V_OUT
5 GND
4 AV_DD/V_REF
Table 1. PIN DESCRIPTION
PIN
NAME
DESCRIPTION
Level-triggered control input (active low). This is the frame sychronization signal for the input data. When
SYNC goes low, it enables the input shift register and data are transferred in on the falling edges of the
1
SYNC
following clocks. The DAC is updated following 16th clock cycle, unless SYNC is taken high before this
edge, in which case the rising edge of SYNC acts as an interrupt and the write sequence is ignored by
the DACx311. Refer to the SYNC Interrupt section for more details.
2
SCLK
Serial Clock Input. Data can be transferred at rates up to 50MHz.
3
D_IN
Serial Data Input. Data is clocked into the 16-bit input shift register on the falling edge of the serial clock
input.
4
AV_DD/V_REF Power Supply Input, +1.8V to 5.5V.
5
GND
Ground reference point for all circuitry on the part.
6
V_OUT
Analog output voltage from DAC. The output amplifier has rail-to-rail operation.
Copyright © 2008–2011, Texas Instruments Incorporated
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