ADS5411IPGPR_14 Datasheet, PDF (5/25 Pages) Texas Instruments – 11 Bit, 105 MSPS Analog-to-Digital Converter

ADS5411
www.ti.com
SLAS487A − SEPTEMBER 2005 − REVISED JANUANRY 2010
TIMING CHARACTERISTICS⁽³⁾
Over full temperature range, AV_DD = 5 V, DRV_DD = 3.3 V, sampling rate = 105 MSPS
PARAMETER
DESCRIPTION
Aperture Time
t_A
t_J
k_J
Clock Input
Aperture delay
Clock slope independent aperture uncertainty (jitter)
Clock slope dependent jitter factor
t_CLK
Clock period
t_CLKH(1)
Clock pulse width high
t_CLKL(1)
Clock pulse width low
Clock to DataReady (DRY)
t_DR
Clock rising 50% to DRY falling 50%
t_{C_DR}
Clock rising 50% to DRY rising 50%
t_{C_DR_50%}
Clock rising 50% to DRY rising 50% with 50% duty cycle clock
Clock to DATA, OVR⁽⁴⁾
t_r
Data V_OL to data V_OH (rise time)
t_f
Data V_OH to data V_OL (fall time)
L
Latency
t_su(C)
Valid DATA⁽²⁾ to clock 50% with 50% duty cycle clock (setup time)
t_H(C)
Clock 50% to invalid DATA⁽²⁾ (hold time)
DataReady (DRY) to DATA, OVR⁽⁴⁾
t_{su(DR)_50%}
Valid DATA⁽²⁾ to DRY 50% with 50% duty cycle clock (setup time)
t_{h(DR)_50%}
DRY 50% to invalid DATA⁽²⁾ with 50% duty cycle clock (hold time)
(1) _{See Figure 1 for more information.}
(2) _{See VOH and VOL levels.}
(3) _{All values obtained from design and characterization.}
(4) _{Data is updated with clock rising edge or DRY falling edge.}
MIN TYP MAX UNIT
500
ps
150
fs
50
µV
9.5
ns
4.75
ns
4.75
ns
2.8 3.9 4.7
ns
t_DR +
t_CLKH
ns
7.6 8.7 9.5
ns
2
2
3
1.8 3.4
2.6 3.6
ns
ns
Cycles
ns
ns
1.6 2.6
ns
3.9 4.4
ns
t_A
N+3
N
AIN
CLK, CLK
D[13:0], OVR
DRY
N+1
N+2
t_CLK
N
t_r
t_CLKH
N+1
N−3
t_f
t_CLKL
N−2
N+2
t_{C_DR}
t_su(DR)
N+3
N−1
t_h(DR)
t_DR
Figure 1. Timing Diagram
N+4
t_su(C)
N
N+4
t_h(C)
5