ADS5409 Datasheet, PDF (5/41 Pages) Texas Instruments – Dual Channel 12-Bit 900Msps Analog-to-Digital Converter

ADS5409
www.ti.com
PRODUCT
PACKAGE-
LEAD
PACKAGE
DESIGNATOR
ADS5409
196-BGA
ZAY
PACKAGE/ORDERING INFORMATION
SPECIFIED
TEMPERATURE
RANGE
ECO
PLAN⁽²⁾
LEAD/
BALL
FINISH
PACKAGE
MARKING
–40C to 85C
GREEN
(RoHS & no
Sb/Br)
ADS5409I
SLAS935 – MAY 2013
ORDERING
NUMBER
ADS5409IZAY
ADS5409IZAYR
TRANSPORT
MEDIA,
QUANTITY
Tray
Tape and Reel
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)⁽¹⁾
Supply voltage range, AVDD33
Supply voltage range, AVDDC
Supply voltage range, AVDD18
Supply voltage range, DVDD
Supply voltage range, DVDDLVDS
Supply voltage range, IOVDD
INA/B_P, INA/B_N
CLKINP, CLKINN
Voltage applied to input pins
SYNCP, SYNCN
SRESET, SDENB, SCLK, SDIO, SDO, ENABLE
Operating free-air temperature range, T_A
Operating junction temperature range, T_J
Storage temperature range
ESD, Human Body Model
VALUE
MIN
MAX
–0.5
4
–0.5
2.3
–0.5
2.3
–0.5
2.3
–0.5
2.3
–0.5
4
–0.5
AVDD33 + 0.5
–0.5
AVDDC + 0.5
–0.5
AVDD33 + 0.5
–0.5
IOVDD + 0.5
–40
85
150
–65
150
2
UNIT
V
V
V
V
V
V
V
V
V
V
°C
°C
°C
kV
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
THERMAL INFORMATION
THERMAL METRIC⁽¹⁾
θ_JA
θ_JCtop
θ_JB
ψ_JT
ψ_JB
θ_JCbot
Junction-to-ambient thermal resistance⁽²⁾
Junction-to-case (top) thermal resistance⁽³⁾
Junction-to-board thermal resistance⁽⁴⁾
Junction-to-top characterization parameter⁽⁵⁾
Junction-to-board characterization parameter⁽⁶⁾
Junction-to-case (bottom) thermal resistance⁽⁷⁾
ADS5409
nFBGA
196 PINS
37.6
6.8
16.8
0.2
16.4
N/A
UNITS
°C/W
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
(2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
(3) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-
standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(4) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
(5) The junction-to-top characterization parameter, ψ_JT, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θ_JA, using a procedure described in JESD51-2a (sections 6 and 7).
(6) The junction-to-board characterization parameter, ψ_JB, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θ_JA , using a procedure described in JESD51-2a (sections 6 and 7).
(7) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
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