ADC121S705 Datasheet, PDF (5/31 Pages) Texas Instruments – 12-Bit, 500 kSPS to 1 MSPS, Differential Input, Micro Power A/D Converter

ADC121S705
www.ti.com
SNAS355B – DECEMBER 2006 – REVISED MARCH 2013
ADC121S705 Converter Electrical Characteristics⁽¹⁾ (continued)
The following specifications apply for V_A = +4.5V to 5.5V, V_REF = 2.5V, f_SCLK = 8 to 16 MHz, f_IN = 100 kHz, C_L = 25 pF, unless
otherwise noted. Boldface limits apply for T_A = T_MIN to T_MAX; all other limits are at T_A = 25°C.
Symbol
Parameter
Conditions
Typical
Limits
Units ⁽²⁾
POWER SUPPLY CHARACTERISTICS
V_A
Analog Supply Voltage
4.5
V (min)
5.5
V (max)
I_VA
Supply Current, Normal Mode
(Normal) (Operational)
I_VA (PD)
Supply Current, Power Down Mode (CS
high)
PWR
Power Consumption, Normal Mode
(Normal) (Operational)
PWR
(PD)
PSRR
Power Consumption, Power Down Mode
(CS high)
Power Supply Rejection Ratio
f_SCLK = 16 MHz, f_S = 1 MSPS,
f_IN = 100 kHz
f_SCLK = 8 MHz, f_S = 500 kSPS,
f_IN = 100 kHz
f_SCLK = 16 MHz
f_SCLK = 0 ⁽³⁾
f_SCLK = 16 MHz, f_S = 1 MSPS,
f_IN = 100 kHz, V_A = 5.0V
f_SCLK = 8 MHz, f_S = 500 kSPS,
f_IN = 100 kHz, V_A = 5.0V
f_SCLK = 16 MHz, V_A = 5.0V
f_SCLK = 0, V_A = 5.0V
See the Specification Definitions for the
test condition
2.3
1.8
56
0.3
11.5
9.0
280
1.5
−85
3
mA (max)
mA
µA (max)
2
µA (max)
mW
mW
µW
µW
dB
AC ELECTRICAL CHARACTERISTICS
f_SCLK
f_SCLK
f_S
t_ACQ
Maximum Clock Frequency
Minimum Clock Frequency
Maximum Sample Rate⁽⁴⁾
Track/Hold Acquisition Time
20
16
MHz (min)
0.8
8
MHz (max)
1.25
1
MSPS (min)
2.5
SCLK cycles
(min)
3.0
SCLK cycles
(max)
t_CONV
t_AD
Conversion Time
Aperture Delay
See Specification Definitions
13
SCLK cycles
6
ns
(3) Data sheet min/max specification limits are specified by design, test, or statistical analysis.
(4) While the maximum sample rate is f_SCLK/16, the actual sample rate may be lower than this by having the CS rate slower than f_SCLK/16.
ADC121S705 Timing Specifications⁽¹⁾
The following specifications apply for V_A = +4.5V to 5.5V, V_REF = 2.5V, f_SCLK = 8 MHz to 16 MHz, C_L = 25 pF, Boldface limits
apply for T_A = T_MIN to T_MAX: all other limits T_A = 25°C.
Symbol
Parameter
Conditions
Typical
Limits
Units
t_CSH
t_CSSU
t_DH
t_DA
t_DIS
t_EN
t_CH
t_CL
t_r
t_f
CS Hold Time after an SCLK rising edge
CS Setup Time prior to an SCLK rising edge
D_OUT Hold time after an SCLK Falling edge
D_OUT Access time after an SCLK Falling edge
D_OUT Disable Time after the rising edge of CS⁽²⁾
D_OUT Enable Time after the falling edge of CS
SCLK High Time
SCLK Low Time
D_OUT Rise Time
D_OUT Fall Time
5
ns (min)
5
ns (min)
7
2.5
ns (min)
18
22
ns (max)
20
ns (max)
8
20
ns (max)
25
ns (min)
25
ns (min)
7
ns
7
ns
(1) Data sheet min/max specification limits are specified by design, test, or statistical analysis.
(2) t_DIS is the time for D_OUT to change 10% while being loaded by the Timing Test Circuit.
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