TLV320ADC3101 Datasheet, PDF (48/92 Pages) Texas Instruments – Low Power Stereo ADC for Wireless Handsets and Portable Audio

TLV320ADC3101
SLAS553B – NOVEMBER 2008 – REVISED AUGUST 2015
BIT
D7–D0
READ/
WRITE
R
Table 24. Page 0 / Register 9 Through Page 0 / Register 17: Reserved
RESET
VALUE
XXXX XXXX Reserved. Do not write to these registers.
DESCRIPTION
BIT READ/
WRITE
D7
R/W
D6–D0 R/W
Table 25. Page 0 / Register 18: ADC NADC Clock Divider
RESET
VALUE
0
000 0001
NADC Clock Divider Power Control:
0: NADC clock divider is powered down
1: NADC clock divider is powered up
NADC Value:
000 0000: NADC clock divider = 128
000 0001: NADC clock divider = 1
000 0010: NADC clock divider = 2
...
111 1110: NADC clock divider = 126
111 1111: NADC clock divider = 127
DESCRIPTION
BIT READ/
WRITE
D7
R/W
D6–D0 R/W
Table 26. Page 0 / Register 19: ADC MADC Clock Divider
RESET
VALUE
0
000 0001
DESCRIPTION
0: ADC MADC clock divider is powered down
1: ADC MADC clock divider is powered up
000 0000: MADC clock divider = 128
000 0001: MADC clock divider = 1
000 0010: MADC clock divider = 2
...
111 1110: MADC clock divider = 126
111 1111: MADC clock divider = 127
BIT
READ/
WRITE
D7–D0 R/W
RESET
VALUE
1000 0000
Table 27. Page 0 / Register 20: ADC AOSR⁽¹⁾
ADC Oversampling Value (AOSR):
0000 0000: AOSR = 256
0000 0001: AOSR = 1
0000 0010: AOSR = 2
...
1111 1110: AOSR = 254
1111 1111: AOSR = 255
DESCRIPTION
(1) AOSR must be an integral multiple of the ADC decimation factor.
BIT
READ/
WRITE
D7–D0 R/W
RESET
VALUE
1000 0000
Table 28. Page 0 / Register 21: ADC IADC⁽¹⁾
DESCRIPTION
0000 0000: Reserved. Do not use.
Number of instructions for ADC miniDSP (IADC):
0000 0001: IADC = 2
0000 0010: IADC = 4
...
1011 1111: IADC = 382
1100 0000: IADC = 384
1100 0001–1111 1111: IADC = up to 510
(1) IADC must be an integral multiple of the ADC decimation factor.
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