TAS5548 Datasheet, PDF (48/116 Pages) Texas Instruments – 8-Channel HD Compatible Audio Processor with ASRC and PWM Output

TAS5548
SLES270A – NOVEMBER 2012 – REVISED APRIL 2015
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7.4.21.7 Modulation Index Limit
PWM modulation is a linear function of the audio signal. When the audio signal is 0, the PWM modulation is
50%. When the audio signal increases toward full scale, the PWM modulation increases toward 100%. For
negative signals, the PWM modulations fall below 50% toward 0%.
However, the maximum possible modulation does have a limit. During the off time period, the power stage
connected to the TAS5548 output needs to get ready for the next on-time period. The maximum possible
modulation is then set by the power stage requirements. The default modulation index limit setting is 93.7%;
however, some power stages may require a lower modulation limit. See the applicable power stage data sheet
for details on setting the modulation index limit. The default setting of 93.7% can be changed in the modulation
index register (0x16).
7.4.22 Master Clock and Serial Data Rate Controls
On the TAS5548 the internal master clock is derived from the XTAL and the internal sampling rate will always be
96 kHz (double speed mode) or 192 kHz (quad speed mode).
The TAS5548 can detect MCLK and the data rate automatically.
The MCLK frequency can be 64 f_S, 128 f_S, 196 f_S, 256 f_S, 384 f_S, 512 f_S, or 768 f_S.
The TAS5548 accepts a 64 f_S SCLK rate and a 1 f_S LRCLK.
The clock and serial data interface have several control parameters:
• MCLK ratio (64 f_S, 128 f_S, 196 f_S, 256 f_S, 384 f_S, 512 f_S, or 768 f_S) – I²C parameter
• Data rate (32, 44.1, 48, 88.2, 96, 176.4, 192 kHz) – I²C parameter
• AM mode enable/disable – I²C parameter
7.4.22.1 192kHz Native Processing Mode
The TAS5548 ASRC defaults to 96kHz at startup. This means all DAP processing and filter calculations should
be based on 96kHz sample rate.
However, the TAS5548 is also capable of processing content at 192kHz (with a reduced channel count).
To enable 192kHz native mode
• Write to 0xC5 ASRC Mode Control
• Set D20 = 1 (Serial clock output sampling rate is the internal sampling rate)
• Set D1:0 = 01 (192kHz Sampling Rate)
• 0xC5 = 0011 0001
DAP processing and filter calculations should be based on 192kHz sample rate. This mode should be used with
an incoming I2S rate of 192kHz
7.4.22.2 PLL Operation
The TAS5548 uses two internal clocks generated by two internal phase-locked loops (PLLs), the digital PLL
(DPLL) and the analog PLL (APLL). The APLL provides the reference clock for the PWM. The DPLL provides the
reference clock for the digital audio processor and the control logic.
The XTAL input provides the input reference clock for the APLL. The external crystal provides a time base to
support a number of operations, including the detection of the MCLK ratio, the data rate, and clock error
conditions. The internal oscillator time base provides a constant rate for all controls and signal timing.
7.5 Programming
7.5.1 I²C Serial-Control Interface (Slave Addresses 0x36)
The TAS5548 has a bidirectional I²C interface that is compatible with the Inter-IC (I²C) bus protocol and supports
both 100-kbps and 400-kbps data transfer rates for single- and multiple-byte write and read operations. This is a
slave-only device that does not support a multimaster bus environment or wait state insertion. The control
interface is used to program the registers of the device and to read device status.
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