AFE032 Datasheet, PDF (48/77 Pages) Texas Instruments – Power-Line Communications Analog Front-End

AFE032
SBOS669A – AUGUST 2013 – REVISED DECEMBER 2013
Table 26. REG_DIG_ERROR Register (Address = 0Dh)
7
6
5
4
3
2
Reserved
Reserved
AFIFO overflow
SPI write
address fail
SPI illegal
access
SPI address
error
R0
R0
R0
R0
R0
R0
LEGEND: R = read-only; R0 = read '0' (these bits reset to '0' after being read).
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1
0
Reserved
R
This register is comprised of digital logic error detection bits. All bits are reset to '0' when read.
Bits[7:6]
Bit 5
Bit 4
Bit 3
Bit 2
Bits 1:0
Reserved
Reserved
Default = 0
AFIFO overflow
SPI and DAC ASYNCH FIFO overflow.
0 = Normal operation (default)
1 = Error detected
SPI write address fail
An error indicates that a read-only register was attempted to be written to.
0 = Normal operation (default)
1 = Error detected
SPI illegal access
An error indicates that a register reserved for factory testing and trimming was attempted to be written to.
0 = Normal operation (default)
1 = Error detected
SPI address error
An error indicates that either a nonexistent register, a reserved register, or a read-only register was attempted to be
written to.
0 = Normal operation (default)
1 = Error detected
Reserved
These bits are reserved.
Default = 0
7
6
Die_ID
R
LEGEND: R = read-only.
Table 27. REG_ID Register (Address = 0Eh)
5
4
3
2
1
0
Revision
Reserved
R
R
Bits[7:6]
Bits[5:3]
Bits[2:0]
Die_ID
These bits are the die identification.
Default = 0
Revision
These bits are the revision indicator.
Default = 0
Reserved
These bits are reserved.
Default = 0
48
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