TM4C1233H6PM Datasheet, PDF (470/1215 Pages) Texas Instruments – Tiva Microcontroller

Hibernation Module
Table 7-1. Hibernate Signals (64LQFP) (continued)
Pin Name
Pin Number Pin Mux / Pin Pin Type Buffer Type^a Description
Assignment
XOSC0
34
fixed
I
Analog Hibernation module oscillator crystal input or an
external clock reference input. Note that this is
either a 32.768-kHz crystal or a 32.768-kHz
oscillator for the Hibernation module RTC.
XOSC1
36
fixed
O
Analog Hibernation module oscillator crystal output. Leave
unconnected when using a single-ended clock
source.
a. The TTL designation indicates the pin has TTL-compatible voltage levels.
7.3 Functional Description
The Hibernation module provides two mechanisms for power control:
■ The first mechanism uses internal switches to control power to the Cortex-M4F as well as to
most analog and digital functions while retaining I/O pin power (VDD3ON mode).
■ The second mechanism controls the power to the microcontroller with a control signal (HIB) that
signals an external voltage regulator to turn on or off.
The Hibernation module power source is determined dynamically. The supply voltage of the
Hibernation module is the larger of the main voltage source (V_DD) or the battery/auxilliary voltage
source (V_BAT). The Hibernation module also has an independent clock source to maintain a real-time
clock (RTC) when the system clock is powered down. Hibernate mode can be entered through one
of two ways:
■ The user initiates hibernation by setting the HIBREQ bit in the Hibernation Control (HIBCTL)
register
7.3.1
■ Power is arbitrarily removed from V_DD while a valid V_BAT is applied
Once in hibernation, the module signals an external voltage regulator to turn the power back on
when an external pin (WAKE) is asserted or when the internal RTC reaches a certain value. The
Hibernation module can also detect when the battery voltage is low and optionally prevent hibernation
or wake from hibernation when the battery voltage falls below a certain threshold.
When waking from hibernation, the HIB signal is deasserted. The return of V_DD causes a POR to
be executed. The time from when the WAKE signal is asserted to when code begins execution is
equal to the wake-up time (t_{WAKE_TO_HIB}) plus the power-on reset time (T_POR).
Register Access Timing
Because the Hibernation module has an independent clocking domain, hibernation registers must
be written only with a timing gap between accesses. The delay time is t_{HIB_REG_ACCESS}, therefore
software must guarantee that this delay is inserted between back-to-back writes to Hibernation
registers or between a write followed by a read. The WC interrupt in the HIBMIS register can be used
to notify the application when the Hibernation modules registers can be accessed. Alternatively,
software may make use of the WRC bit in the Hibernation Control (HIBCTL) register to ensure that
the required timing gap has elapsed. This bit is cleared on a write operation and set once the write
completes, indicating to software that another write or read may be started safely. Software should
poll HIBCTL for WRC=1 prior to accessing any hibernation register.
470
June 12, 2014
Texas Instruments-Production Data