TPS53851 Datasheet, PDF (47/64 Pages) Texas Instruments – DUAL OR 2-PHASE, STACKABLE CONTROLLER

TPS53851
www.ti.com
SLUS985 – DECEMBER 2009
6.1.5.11 CLKIO (pin 28)
CLKIO is floating as no clock synchronization required for dual output configuration.
6.1.5.12 BOOT1 and SW1 (pin 27 and 25)
A bootstrap capacitor is connected between the BOOT1 and SW1 pin. The bootstrap capacitor depends
on the total gate charge of the high side MOSFET and the amount of droop allowed on the bootstrap
capacitor.
C_boot
=
Qg
ΔV
=
8nc
0.5V
= 16nF
(44)
For this application, a 0.1-μF capacitor is selected.
6.1.5.13 TRK1 (pin 33)
A 22-nF capacitor is tied to TRK1 pin to provide 1.28 ms soft start time.
Tss = Css × 58 × 10³ = 22 × 10^-9 × 58 × 10³ = 1.28m s
(45)
6.1.5.14 DIFFO, VOUT and GSNS (pin 1, pin 2 and pin 3)
VOUT and GSNS are connected to the remote sensing output connector. DIFFO is connected to the
feedback resistor divider. If the differential amplifier is not used, VOUT and GSNS are suggested to be
grounded, and DIFFO is left open.
6.1.6 Feedback Compensator Design (COMP1 pin 35)
Peak current mode control method is employed in the controller. A small signal model is developed from
the COMP signal to the output.
Gvc(s) =
1
× ¹ × ^{(s × COUT × ESR + 1) × ROUT}
DCR × Ac s × τ_s + 1
s × C_OUT × R_OUT + 1
(46)
The time constant is defined by:
τ_s =
T
V_{ramp - VOUT × DCR × Ac}
ln(
V_ramp
-
V_IN
-
TL
V_{OUT × DCR × Ac}
-
2 × V_OUT
)
× DCR × Ac
T
L
L
(47)
The low frequency pole is calculated by:
1
f=
= 2.36kHz
VCP1 _{2 × π × C × R}
OUT
OUT
(48)
The ESR zero is calculated by:
1
f=
= 176.8kHz
ESR _{2 × π × C × ESR}
OUT
(49)
In this design, a Type II compensator is employed to compensate the loop.
Copyright © 2009, Texas Instruments Incorporated
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DESIGN EXAMPLES
47